From 1cca1563c64cd521a384a5df404dbccb3e06cb5c Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Tue, 18 Oct 2016 20:46:49 -0700 Subject: [PATCH] Fixed typo in last commit --- techlibs/greenpak4/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 76bf058d2..80746be0f 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -308,7 +308,7 @@ endmodule module GP_PGEN(input wire nRST, input wire CLK, output reg OUT); initial OUT = 0; parameter PATTERN_DATA = 16'h0; - parameter PATTERN_LEN = 4'd16; + parameter PATTERN_LEN = 5'd16; reg[3:0] count = 0; always @(posedge CLK) begin -- 2.30.2