From 1cce9a0d566f33b96b0303d133d42778cf1bdcdf Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 21 Aug 2020 13:06:03 +0100
Subject: [PATCH] first test of down-converted load/store from 64 to 32 bit

---
 src/soc/bus/test/test_minerva.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py
index d70655ff..5d784b1f 100644
--- a/src/soc/bus/test/test_minerva.py
+++ b/src/soc/bus/test/test_minerva.py
@@ -12,7 +12,7 @@ class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit):
                 isinstance(pspec.dmem_test_depth, int)):
             depth = pspec.dmem_test_depth
         else:
-            depth = 32
+            depth = 64
         print("TestSRAMBareLoadStoreUnit depth", depth)
 
         self.mem = Memory(width=self.data_wid, depth=depth)
-- 
2.30.2