From 1ccf6a55ec5b0b99c166e0b047c325e8332701d0 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Fri, 5 Jun 2020 16:01:41 +0200 Subject: [PATCH] implement init function of DualPortSplitter --- src/soc/experiment/l0_cache.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index bff6958a..1e85beae 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -113,7 +113,7 @@ class PortInterface(RecordObject): self.ld = Data(regwid, "ld_data_o") # ok to be set by L0 Cache/Buf self.st = Data(regwid, "st_data_i") # ok to be set by CompUnit -# TODO: +# TODO: elaborate function class DualPortSplitter(Elaboratable): @@ -129,7 +129,11 @@ class DualPortSplitter(Elaboratable): once that is done each pair of ports may be wired directly to the dual ports of L0CacheBuffer """ - pass + def __init__(self): + self.outp = [] + self.outp[0] = PortInterface(name="outp_0") + self.outp[1] = PortInterface(name="outp_1") + self.inp = PortInterface(name="inp") class DataMergerRecord(Record): -- 2.30.2