From 1cd6c71826d568b467a4ccfdd40fab2f61c3efe3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 19 Jun 2020 22:30:01 +0100 Subject: [PATCH] whitespace update --- src/soc/fu/div/pipe_data.py | 4 ++-- src/soc/fu/div/pipeline.py | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py index f9df4e56..0b34a297 100644 --- a/src/soc/fu/div/pipe_data.py +++ b/src/soc/fu/div/pipe_data.py @@ -26,8 +26,8 @@ class CoreBaseData(ALUInputData): self.dividend_neg = Signal(reset_less=True) self.div_by_zero = Signal(reset_less=True) - # set if an overflow for divide extended instructions is detected because - # `abs_dividend >= abs_divisor` for the appropriate bit width; + # set if an overflow for divide extended instructions is detected + # because `abs_dividend >= abs_divisor` for the appropriate bit width; # 0 if the instruction is not a divide extended instruction self.dive_abs_overflow_32 = Signal(reset_less=True) self.dive_abs_overflow_64 = Signal(reset_less=True) diff --git a/src/soc/fu/div/pipeline.py b/src/soc/fu/div/pipeline.py index fb510ff0..c503f14b 100644 --- a/src/soc/fu/div/pipeline.py +++ b/src/soc/fu/div/pipeline.py @@ -3,7 +3,8 @@ from nmutil.pipemodbase import PipeModBaseChain from soc.fu.alu.input_stage import ALUInputStage from soc.fu.alu.output_stage import ALUOutputStage from soc.fu.div.setup_stage import DivSetupStage -from soc.fu.div.core_stages import DivCoreSetupStage, DivCoreCalculateStage, DivCoreFinalStage +from soc.fu.div.core_stages import (DivCoreSetupStage, DivCoreCalculateStage, + DivCoreFinalStage) from soc.fu.div.output_stage import DivOutputStage -- 2.30.2