From 1cde473ec08e9aa60f474d460df1b4c3ba6d3c70 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 17 May 2017 02:45:25 +0200 Subject: [PATCH] radeonsi: remove CE offset alignment restriction MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This was only needed by LOAD_CONST_RAM, which is now only used to load whole CE. Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_descriptors.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index b514961925f..5086a33969a 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -113,8 +113,7 @@ static void si_init_descriptors(struct si_descriptors *desc, desc->uses_ce = true; desc->ce_offset = *ce_offset; - /* make sure that ce_offset stays 32 byte aligned */ - *ce_offset += align(element_dw_size * num_elements * 4, 32); + *ce_offset += element_dw_size * num_elements * 4; } } -- 2.30.2