From 1ced826c8ef94f19b301839d4377cb3eba746de9 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 3 May 2020 14:16:28 +0100
Subject: [PATCH] add walkthrough video for memory and cache

---
 3d_gpu/architecture/memory_and_cache.mdwn | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/3d_gpu/architecture/memory_and_cache.mdwn b/3d_gpu/architecture/memory_and_cache.mdwn
index da2caaf3e..19695e3d9 100644
--- a/3d_gpu/architecture/memory_and_cache.mdwn
+++ b/3d_gpu/architecture/memory_and_cache.mdwn
@@ -6,6 +6,8 @@ expected to run at one-to-one from an external 24 mhz to 100 mhz clock.
 The requirements are therefore **radically different** from the next
 roadmap ASIC.
 
+Walkthrough video: <https://youtu.be/6Yiyw4abJpE>
+
 Basic diagram:
 
 [[!img 180nm_single_core_testasic_memlayout.jpg size="600x"]]
-- 
2.30.2