From 1d053bd7eee82c72740699149827db8f8c6b481f Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 25 Sep 2014 15:37:49 +0200
Subject: [PATCH] modify TestDesign to be able to simulate phy with host <-->
 device loopback

---
 platforms/kc705_impact.py | 29 +++++++++++++++++++----------
 targets/test.py           |  3 ++-
 2 files changed, 21 insertions(+), 11 deletions(-)

diff --git a/platforms/kc705_impact.py b/platforms/kc705_impact.py
index fb92c3ef..465db288 100644
--- a/platforms/kc705_impact.py
+++ b/platforms/kc705_impact.py
@@ -34,31 +34,31 @@ _io = [
 	("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")),
 	("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")),
 	("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
-	
+
 	("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")),
-	
+
 	("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")),
 	("user_btn_n", 0, Pins("AA12"), IOStandard("LVCMOS15")),
 	("user_btn_s", 0, Pins("AB12"), IOStandard("LVCMOS15")),
 	("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")),
 	("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")),
-	
+
 	("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")),
 	("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")),
 	("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")),
 	("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")),
-	
+
 	("clk200", 0,
 		Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
 		Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
 	),
-	
+
 	("clk156", 0,
 		Subsignal("p", Pins("K28"), IOStandard("LVDS_25")),
 		Subsignal("n", Pins("K29"), IOStandard("LVDS_25"))
 	),
-	
-	
+
+
 	("serial", 0,
 		Subsignal("cts", Pins("L27")),
 		Subsignal("rts", Pins("K23")),
@@ -66,8 +66,17 @@ _io = [
 		Subsignal("rx", Pins("M19")),
 		IOStandard("LVCMOS25")
 	),
-	
-	("sata", 0,
+
+	("sata_host", 0,
+		Subsignal("refclk_p", Pins("YYY")),
+		Subsignal("refclk_n", Pins("YYY")),
+		Subsignal("txp", Pins("YYY")),
+		Subsignal("txn", Pins("YYY")),
+		Subsignal("rxp", Pins("YYY")),
+		Subsignal("rxn", Pins("YYY")),
+	),
+
+	("sata_device", 0,
 		Subsignal("refclk_p", Pins("YYY")),
 		Subsignal("refclk_n", Pins("YYY")),
 		Subsignal("txp", Pins("YYY")),
@@ -102,5 +111,5 @@ def Platform(*args, toolchain="vivado", **kwargs):
 			try:
 				self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
 			except ConstraintError:
-				pass			
+				pass
 	return RealPlatform(*args, **kwargs)
diff --git a/targets/test.py b/targets/test.py
index f30c66b2..c1dd7522 100644
--- a/targets/test.py
+++ b/targets/test.py
@@ -94,6 +94,7 @@ class TestDesign(UART2WB):
 		UART2WB.__init__(self, platform, clk_freq)
 		self.submodules.crg = _CRG(platform)
 
-		self.submodules.sataphy = K7SATAPHY(platform.request("sata"))
+		self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), host=True)
+		self.submodules.sataphy_device = K7SATAPHY(platform.request("sata_device"), host=False)
 
 default_subtarget = TestDesign
-- 
2.30.2