From 1d07d413198096e143f51d177d2f0f13cf652a82 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 30 Sep 2018 09:26:54 +0100 Subject: [PATCH] update template comment --- riscv/insn_template_sv.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc index c2f4b1a..92404e5 100644 --- a/riscv/insn_template_sv.cc +++ b/riscv/insn_template_sv.cc @@ -8,10 +8,10 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc) int xlen = ISASZ; reg_t npc = sext_xlen(pc + insn_length(INSNCODE)); // messy way to do it: insn_t is used elsewhere in a union, - // so a workaround is to grab the bits from the insn_t + // so cannot create virtual functions. + // a workaround is to grab the bits from the insn_t // and create an sv-variant. also an opportunity to pass - // in the loop index (voffs) which will be added on to - // any registers that are marked as "vectorised" + // in a stack of other things that are needed. insn_bits_t bits = s_insn.bits(); #ifndef USING_NOREGS int vlen = p->get_state()->vl; -- 2.30.2