From 1d1eccbdc9a9cefb8d9451d9ba646752b687211f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 10 Mar 2020 19:49:55 +0000 Subject: [PATCH] initial test LD comp unit in scoreboard --- src/soc/experiment/compldst.py | 2 ++ src/soc/experiment/score6600.py | 22 ++++++++++++++-------- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/src/soc/experiment/compldst.py b/src/soc/experiment/compldst.py index f8b27525..50137c32 100644 --- a/src/soc/experiment/compldst.py +++ b/src/soc/experiment/compldst.py @@ -387,6 +387,8 @@ def add(dut, src1, src2, imm, imm_mode = False): return data def scoreboard_sim(dut): + data = yield from load(dut, 4, 0, 2) + return # two STs (different addresses) yield from store(dut, 4, 3, 2) yield from store(dut, 2, 9, 2) diff --git a/src/soc/experiment/score6600.py b/src/soc/experiment/score6600.py index f720ecfb..cc85ac50 100644 --- a/src/soc/experiment/score6600.py +++ b/src/soc/experiment/score6600.py @@ -549,9 +549,9 @@ class Scoreboard(Elaboratable): # issue_i. multi-issue gets a bit more complex but not a lot. prior_ldsts = Signal(cul.n_units, reset_less=True) sync += prior_ldsts.eq(memfus.g_int_ld_pend_o | memfus.g_int_st_pend_o) - with m.If(self.ls_oper_i[2]): # LD bit of operand + with m.If(self.ls_oper_i[3]): # LD bit of operand comb += memfus.ld_i.eq(cul.issue_i | prior_ldsts) - with m.If(self.ls_oper_i[3]): # ST bit of operand + with m.If(self.ls_oper_i[2]): # ST bit of operand comb += memfus.st_i.eq(cul.issue_i | prior_ldsts) # TODO: adr_rel_o needs to go into L1 Cache. for now, @@ -567,7 +567,7 @@ class Scoreboard(Elaboratable): go_st_i = Signal(cul.n_units, reset_less=True) go_ld_i = Signal(cul.n_units, reset_less=True) comb += go_ld_i.eq(memfus.loadable_o & memfus.addr_nomatch_o &\ - cul.req_rel_o & cul.ld_o) + cul.adr_rel_o & cul.ld_o) comb += go_st_i.eq(memfus.storable_o & memfus.addr_nomatch_o &\ cul.sto_rel_o & cul.st_o) comb += memfus.go_ld_i.eq(go_ld_i) @@ -610,7 +610,13 @@ class Scoreboard(Elaboratable): # Connect Picker #--------- comb += intpick1.rd_rel_i[0:n_intfus].eq(cu.rd_rel_o[0:n_intfus]) - comb += intpick1.req_rel_i[0:n_intfus].eq(cu.req_rel_o[0:n_intfus]) + #comb += intpick1.req_rel_i[0:n_intfus].eq(cu.req_rel_o[0:n_intfus]) + # HACK for now: connect LD/ST request release to *address* release + comb += intpick1.req_rel_i[0].eq(cu.req_rel_o[0]) # ALU 0 + comb += intpick1.req_rel_i[1].eq(cu.req_rel_o[1]) # ALU 1 + comb += intpick1.req_rel_i[2].eq(cul.adr_rel_o[0]) # LD/ST 0 + comb += intpick1.req_rel_i[3].eq(cul.adr_rel_o[1]) # LD/ST 1 + comb += intpick1.req_rel_i[4].eq(cu.req_rel_o[4]) # BR 0 int_rd_o = intfus.readable_o int_wr_o = intfus.writable_o comb += intpick1.readable_i[0:n_intfus].eq(int_rd_o[0:n_intfus]) @@ -1125,9 +1131,9 @@ def scoreboard_sim(dut, alusim): # set random values in the registers for i in range(1, dut.n_regs): - val = randint(0, (1<