From 1d4827cbc08b754acb25dc3a4bceca2728fc242a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 21 May 2020 20:35:33 +0100 Subject: [PATCH] move Logical over to use CompLogicalOpSubset --- src/soc/fu/logical/pipe_data.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py index 27e2a694..332fd60e 100644 --- a/src/soc/fu/logical/pipe_data.py +++ b/src/soc/fu/logical/pipe_data.py @@ -2,7 +2,7 @@ from nmigen import Signal, Const from ieee754.fpcommon.getop import FPPipeContext from soc.fu.pipe_data import IntegerData from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec -from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace +from soc.fu.logical.logical_input_record import CompLogicalOpSubset class LogicalInputData(IntegerData): @@ -31,7 +31,6 @@ class LogicalInputData(IntegerData): self.xer_so.eq(i.xer_so)] -# TODO: replace CompALUOpSubset with CompLogicalOpSubset class LogicalPipeSpec(CommonPipeSpec): regspec = (LogicalInputData.regspec, ALUOutputData.regspec) - opsubsetkls = CompALUOpSubset + opsubsetkls = CompLogicalOpSubset -- 2.30.2