From 1d691c18e0190fe2fb30ba8fc5d83a602648a0ab Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 12 Jul 2020 20:46:47 +0100 Subject: [PATCH] change CSV LD/ST update field to LDSTMode (support cix) --- src/soc/decoder/decode2execute1.py | 4 ++-- src/soc/decoder/power_decoder2.py | 2 +- src/soc/decoder/power_enums.py | 7 +++++++ src/soc/experiment/compldst_multi.py | 5 +++-- src/soc/fu/ldst/ldst_input_record.py | 8 ++++---- 5 files changed, 17 insertions(+), 9 deletions(-) diff --git a/src/soc/decoder/decode2execute1.py b/src/soc/decoder/decode2execute1.py index b4f75200..d6b191f0 100644 --- a/src/soc/decoder/decode2execute1.py +++ b/src/soc/decoder/decode2execute1.py @@ -5,7 +5,7 @@ based on Anton Blanchard microwatt decode2.vhdl """ from nmigen import Signal, Record from nmutil.iocontrol import RecordObject -from soc.decoder.power_enums import InternalOp, CryIn, Function, SPR +from soc.decoder.power_enums import InternalOp, CryIn, Function, SPR, LDSTMode class Data(Record): @@ -49,7 +49,7 @@ class Decode2ToOperand(RecordObject): self.data_len = Signal(4, reset_less=True) # bytes self.byte_reverse = Signal(reset_less=True) self.sign_extend = Signal(reset_less=True)# do we need this? - self.update = Signal(reset_less=True) # LD/ST is "update" variant + self.ldst_mode = Signal(LDSTMode, reset_less=True) # LD/ST mode self.traptype = Signal(5, reset_less=True) # see trap main_stage.py self.trapaddr = Signal(13, reset_less=True) self.read_cr_whole = Signal(reset_less=True) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 5f1e99ee..615f78f7 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -644,7 +644,7 @@ class PowerDecode2(Elaboratable): comb += do.byte_reverse.eq(op.br) comb += do.sign_extend.eq(op.sgn_ext) - comb += do.update.eq(op.upd) # LD/ST "update" mode. + comb += do.ldst_mode.eq(op.upd) # LD/ST mode (update, cache-inhibit) # These should be removed eventually comb += do.input_cr.eq(op.cr_in) # condition reg comes in diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py index fd928baf..4ce93591 100644 --- a/src/soc/decoder/power_enums.py +++ b/src/soc/decoder/power_enums.py @@ -257,6 +257,13 @@ class LdstLen(Enum): is8B = 8 +@unique +class LDSTMode(Enum): + NONE = 0 + update = 1 + cix = 2 + + @unique class RC(Enum): NONE = 0 diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py index c1f4f437..2bc00937 100644 --- a/src/soc/experiment/compldst_multi.py +++ b/src/soc/experiment/compldst_multi.py @@ -90,7 +90,7 @@ from soc.experiment.compalu_multi import go_record, CompUnitRecord from soc.experiment.l0_cache import PortInterface from soc.fu.regspec import RegSpecAPI -from soc.decoder.power_enums import InternalOp, Function +from soc.decoder.power_enums import InternalOp, Function, LDSTMode from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset from soc.decoder.power_decoder2 import Data @@ -390,7 +390,8 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): # decode bits of operand (latched) comb += op_is_st.eq(oper_r.insn_type == InternalOp.OP_STORE) # ST comb += op_is_ld.eq(oper_r.insn_type == InternalOp.OP_LOAD) # LD - op_is_update = oper_r.update # UPDATE + op_is_update = oper_r.ldst_mode == LDSTMode.update # UPDATE + op_is_cix = oper_r.ldst_mode == LDSTMode.cix # cache-inhibit comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i) comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i) comb += self.ld_o.eq(op_is_ld) diff --git a/src/soc/fu/ldst/ldst_input_record.py b/src/soc/fu/ldst/ldst_input_record.py index 244f6789..2abf6c22 100644 --- a/src/soc/fu/ldst/ldst_input_record.py +++ b/src/soc/fu/ldst/ldst_input_record.py @@ -1,6 +1,6 @@ from nmigen.hdl.rec import Record, Layout -from soc.decoder.power_enums import InternalOp, Function +from soc.decoder.power_enums import InternalOp, Function, LDSTMode class CompLDSTOpSubset(Record): @@ -23,7 +23,7 @@ class CompLDSTOpSubset(Record): ('data_len', 4), ('byte_reverse', 1), ('sign_extend', 1), - ('update', 1)) + ('ldst_mode', LDSTMode)) Record.__init__(self, Layout(layout), name=name) @@ -35,7 +35,7 @@ class CompLDSTOpSubset(Record): self.data_len.reset_less = True self.byte_reverse.reset_less = True self.sign_extend.reset_less = True - self.update.reset_less = True + self.ldst_mode.reset_less = True def eq_from_execute1(self, other): """ use this to copy in from Decode2Execute1Type @@ -54,6 +54,6 @@ class CompLDSTOpSubset(Record): self.data_len, self.byte_reverse, self.sign_extend, - self.update, + self.ldst_mode, ] -- 2.30.2