From 1d8298af9494836ffb226bcf78ea807b0885d461 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 28 Jun 2017 16:18:15 +0200 Subject: [PATCH] litex/build/sim: add tapcfg submodule for ethernet --- .gitmodules | 3 +++ litex/build/sim/core/modules/ethernet/tapcfg | 1 + 2 files changed, 4 insertions(+) create mode 160000 litex/build/sim/core/modules/ethernet/tapcfg diff --git a/.gitmodules b/.gitmodules index 11034c7d..69988365 100644 --- a/.gitmodules +++ b/.gitmodules @@ -10,3 +10,6 @@ [submodule "litex/soc/cores/cpu/picorv32/verilog"] path = litex/soc/cores/cpu/picorv32/verilog url = https://github.com/cliffordwolf/picorv32 +[submodule "litex/build/sim/core/modules/ethernet/tapcfg"] + path = litex/build/sim/core/modules/ethernet/tapcfg + url = https://github.com/nizox/tapcfg diff --git a/litex/build/sim/core/modules/ethernet/tapcfg b/litex/build/sim/core/modules/ethernet/tapcfg new file mode 160000 index 00000000..4ce399de --- /dev/null +++ b/litex/build/sim/core/modules/ethernet/tapcfg @@ -0,0 +1 @@ +Subproject commit 4ce399deedc42a44f2854b29f8d34ebbd5d45872 -- 2.30.2