From 1db6e702e9f016e4c44a784d78c6894b8d224454 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 11 Nov 2019 16:30:27 -0800 Subject: [PATCH] fastmodel: Implement CC reg accessors. Change-Id: I4d8a7eaa097446b6aa3483880c2a7ed1a2e0d97c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23790 Reviewed-by: Chun-Chen TK Hsu Maintainer: Gabe Black Tested-by: kokoro --- .../arm/fastmodel/CortexA76/thread_context.cc | 50 +++++++++++++++++++ .../arm/fastmodel/CortexA76/thread_context.hh | 4 ++ src/arch/arm/fastmodel/iris/thread_context.cc | 19 +++++++ src/arch/arm/fastmodel/iris/thread_context.hh | 17 ++----- 4 files changed, 78 insertions(+), 12 deletions(-) diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc b/src/arch/arm/fastmodel/CortexA76/thread_context.cc index c7c92d158..281c70aca 100644 --- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc +++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc @@ -93,9 +93,51 @@ CortexA76TC::initFromIrisInstance(const ResourceMap &resources) extractResourceMap(intReg32Ids, resources, intReg32IdxNameMap); extractResourceMap(intReg64Ids, resources, intReg64IdxNameMap); + extractResourceMap(ccRegIds, resources, ccRegIdxNameMap); + extractResourceMap(vecRegIds, resources, vecRegIdxNameMap); } +RegVal +CortexA76TC::readCCRegFlat(RegIndex idx) const +{ + RegVal result = Iris::ThreadContext::readCCRegFlat(idx); + switch (idx) { + case ArmISA::CCREG_NZ: + result = ((CPSR)result).nz; + break; + case ArmISA::CCREG_FP: + result = bits(result, 31, 28); + break; + default: + break; + } + return result; +} + +void +CortexA76TC::setCCRegFlat(RegIndex idx, RegVal val) +{ + switch (idx) { + case ArmISA::CCREG_NZ: + { + CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR); + cpsr.nz = val; + val = cpsr; + } + break; + case ArmISA::CCREG_FP: + { + FPSCR fpscr = readMiscRegNoEffect(ArmISA::MISCREG_FPSCR); + val = insertBits(fpscr, 31, 28, val); + } + break; + default: + break; + } + Iris::ThreadContext::setCCRegFlat(idx, val); +} + iris::MemorySpaceId CortexA76TC::getBpSpaceId(Addr pc) const { @@ -798,6 +840,14 @@ Iris::ThreadContext::IdxNameMap CortexA76TC::intReg64IdxNameMap({ { ArmISA::INTREG_SPX, "SP" }, }); +Iris::ThreadContext::IdxNameMap CortexA76TC::ccRegIdxNameMap({ + { ArmISA::CCREG_NZ, "CPSR" }, + { ArmISA::CCREG_C, "CPSR.C" }, + { ArmISA::CCREG_V, "CPSR.V" }, + { ArmISA::CCREG_GE, "CPSR.GE" }, + { ArmISA::CCREG_FP, "FPSCR" }, +}); + Iris::ThreadContext::IdxNameMap CortexA76TC::vecRegIdxNameMap({ { 0, "V0" }, { 1, "V1" }, { 2, "V2" }, { 3, "V3" }, { 4, "V4" }, { 5, "V5" }, { 6, "V6" }, { 7, "V7" }, diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.hh b/src/arch/arm/fastmodel/CortexA76/thread_context.hh index 5b0ffdbef..af031140c 100644 --- a/src/arch/arm/fastmodel/CortexA76/thread_context.hh +++ b/src/arch/arm/fastmodel/CortexA76/thread_context.hh @@ -43,6 +43,7 @@ class CortexA76TC : public Iris::ThreadContext static IdxNameMap miscRegIdxNameMap; static IdxNameMap intReg32IdxNameMap; static IdxNameMap intReg64IdxNameMap; + static IdxNameMap ccRegIdxNameMap; static IdxNameMap vecRegIdxNameMap; static iris::MemorySpaceId bpSpaceId; @@ -56,6 +57,9 @@ class CortexA76TC : public Iris::ThreadContext void initFromIrisInstance(const ResourceMap &resources) override; + RegVal readCCRegFlat(RegIndex idx) const override; + void setCCRegFlat(RegIndex idx, RegVal val) override; + iris::MemorySpaceId getBpSpaceId(Addr pc) const override; }; diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc b/src/arch/arm/fastmodel/iris/thread_context.cc index b9d34e4bd..c18a5cd7d 100644 --- a/src/arch/arm/fastmodel/iris/thread_context.cc +++ b/src/arch/arm/fastmodel/iris/thread_context.cc @@ -520,6 +520,25 @@ ThreadContext::setIntReg(RegIndex reg_idx, RegVal val) call().resource_write(_instId, result, intReg64Ids.at(reg_idx), val); } +RegVal +ThreadContext::readCCRegFlat(RegIndex idx) const +{ + if (idx >= ccRegIds.size()) + return 0; + iris::ResourceReadResult result; + call().resource_read(_instId, result, ccRegIds.at(idx)); + return result.data.at(0); +} + +void +ThreadContext::setCCRegFlat(RegIndex idx, RegVal val) +{ + panic_if(idx >= ccRegIds.size(), + "CC reg %d is not supported by fast model.", idx); + iris::ResourceWriteResult result; + call().resource_write(_instId, result, ccRegIds.at(idx), val); +} + const ArmISA::VecRegContainer & ThreadContext::readVecReg(const RegId ®_id) const { diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh b/src/arch/arm/fastmodel/iris/thread_context.hh index 77f3ec9fa..5d6827cc9 100644 --- a/src/arch/arm/fastmodel/iris/thread_context.hh +++ b/src/arch/arm/fastmodel/iris/thread_context.hh @@ -83,6 +83,7 @@ class ThreadContext : public ::ThreadContext ResourceIds miscRegIds; ResourceIds intReg32Ids; ResourceIds intReg64Ids; + ResourceIds ccRegIds; iris::ResourceId pcRscId = iris::IRIS_UINT64_MAX; iris::ResourceId icountRscId; @@ -386,7 +387,7 @@ class ThreadContext : public ::ThreadContext RegVal readCCReg(RegIndex reg_idx) const override { - panic("%s not implemented.", __FUNCTION__); + return readCCRegFlat(reg_idx); } void setIntReg(RegIndex reg_idx, RegVal val) override; @@ -419,7 +420,7 @@ class ThreadContext : public ::ThreadContext void setCCReg(RegIndex reg_idx, RegVal val) override { - panic("%s not implemented.", __FUNCTION__); + setCCRegFlat(reg_idx, val); } void pcStateNoRecord(const ArmISA::PCState &val) override { pcState(val); } @@ -547,16 +548,8 @@ class ThreadContext : public ::ThreadContext panic("%s not implemented.", __FUNCTION__); } - RegVal - readCCRegFlat(RegIndex idx) const override - { - panic("%s not implemented.", __FUNCTION__); - } - void - setCCRegFlat(RegIndex idx, RegVal val) override - { - panic("%s not implemented.", __FUNCTION__); - } + RegVal readCCRegFlat(RegIndex idx) const override; + void setCCRegFlat(RegIndex idx, RegVal val) override; /** @} */ }; -- 2.30.2