From 1dcdbdd33c1a192f64c395ce548b300c46d3cd34 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 10 Oct 2021 14:45:46 +0100 Subject: [PATCH] added example with elwidth==Signal(2) from: https://bugs.libre-soc.org/show_bug.cgi?id=713#c30 --- src/ieee754/part/layout_experiment.py | 31 +++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/src/ieee754/part/layout_experiment.py b/src/ieee754/part/layout_experiment.py index e60953e7..a97f47b7 100644 --- a/src/ieee754/part/layout_experiment.py +++ b/src/ieee754/part/layout_experiment.py @@ -5,15 +5,19 @@ Links: https://bugs.libre-soc.org/show_bug.cgi?id=713#c20 """ +from nmigen import Signal, Module, Elaboratable, Mux, Cat, Shape, Repl +from nmigen.back.pysim import Simulator, Delay, Settle +from nmigen.cli import rtlil + from collections.abc import Mapping from pprint import pprint -# stuff to let it run as stand-alone script -def PartitionPoints(pp): - return pp +from ieee754.part_mul_add.partpoints import PartitionPoints + # main fn def layout(elwid, signed, part_counts, lane_shapes): + # identify if the lane_shapes is a mapping (dict, etc.) if not isinstance(lane_shapes, Mapping): lane_shapes = {i: lane_shapes for i in part_counts} part_wid = -min(-lane_shapes[i] // c for i, c in part_counts.items()) @@ -42,6 +46,25 @@ if __name__ == '__main__': for i in range(4): pprint((i, layout(i, True, part_counts, 3))) + l = {0: 5, 1: 6, 2: 12, 3: 24} for i in range(4): - l = {0: 5, 1: 6, 2: 12, 3: 24} pprint((i, layout(i, False, part_counts, l))) + + # https://bugs.libre-soc.org/show_bug.cgi?id=713#c30 + elwid = Signal(2) + pp,b,c,d,e = layout(elwid, False, part_counts, l) + pprint ((pp,b,c,d,e)) + + m = Module() + def process(): + for i in range(4): + yield elwid.eq(i) + yield Settle() + ppt = [] + for pval in list(pp.values()): + val = yield pval # get nmigen to evaluate pp + ppt.append(val) + pprint((i, (ppt,b,c,d,e))) + sim = Simulator(m) + sim.add_process(process) + sim.run() -- 2.30.2