From 1dce798dc5050745490600c09c873d821548f4f7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 25 May 2020 16:39:16 -0700
Subject: [PATCH] tests: add ecp5 latch testcase with -abc9

---
 tests/arch/ecp5/latches_abc9.ys | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 tests/arch/ecp5/latches_abc9.ys

diff --git a/tests/arch/ecp5/latches_abc9.ys b/tests/arch/ecp5/latches_abc9.ys
new file mode 100644
index 000000000..ca3182254
--- /dev/null
+++ b/tests/arch/ecp5/latches_abc9.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module top(input e, d, output q);
+reg l;
+always @*
+    if (e)
+        l = ~d;
+assign q = ~l;
+endmodule
+EOT
+proc
+design -save gold
+
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_ecp5 -abc9
+select -assert-count 2 t:LUT4
+select -assert-none t:LUT4 %% t:* %D
-- 
2.30.2