From 1ddc47c05e80aed3c3ec5b636dd706c0d0264dbc Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Mon, 16 Oct 2017 09:55:32 +0000 Subject: [PATCH] aarch64.h (AARCH64_FL_DOTPROD): New. 2017-10-16 Tamar Christina * config/aarch64/aarch64.h (AARCH64_FL_DOTPROD): New. (AARCH64_ISA_DOTPROD, TARGET_DOTPROD): New. * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add TARGET_DOTPROD. * config/aarch64/aarch64-option-extensions.def (dotprod): New. * config/aarch64/aarch64-cores.def (cortex-a55, cortex-a75): Enable TARGET_DOTPROD. (cortex-a75.cortex-a55): Likewise. * doc/invoke.texi (aarch64-feature-modifiers): Document dotprod. From-SVN: r253782 --- gcc/ChangeLog | 10 ++++++++++ gcc/config/aarch64/aarch64-c.c | 1 + gcc/config/aarch64/aarch64-cores.def | 6 +++--- gcc/config/aarch64/aarch64-option-extensions.def | 8 ++++++-- gcc/config/aarch64/aarch64.h | 15 ++++++++++----- gcc/doc/invoke.texi | 2 ++ 6 files changed, 32 insertions(+), 10 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 499277552bb..f4228ff2385 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2017-10-16 Tamar Christina + + * config/aarch64/aarch64.h (AARCH64_FL_DOTPROD): New. + (AARCH64_ISA_DOTPROD, TARGET_DOTPROD): New. + * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add TARGET_DOTPROD. + * config/aarch64/aarch64-option-extensions.def (dotprod): New. + * config/aarch64/aarch64-cores.def (cortex-a55, cortex-a75): Enable TARGET_DOTPROD. + (cortex-a75.cortex-a55): Likewise. + * doc/invoke.texi (aarch64-feature-modifiers): Document dotprod. + 2017-10-16 Tamar Christina * config/arm/arm-builtins.c (arm_unsigned_uternop_qualifiers): New. diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c index 177e638682f..c7d866f3b56 100644 --- a/gcc/config/aarch64/aarch64-c.c +++ b/gcc/config/aarch64/aarch64-c.c @@ -106,6 +106,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile) aarch64_def_or_undef (TARGET_CRC32, "__ARM_FEATURE_CRC32", pfile); + aarch64_def_or_undef (TARGET_DOTPROD, "__ARM_FEATURE_DOTPROD", pfile); cpp_undef (pfile, "__AARCH64_CMODEL_TINY__"); cpp_undef (pfile, "__AARCH64_CMODEL_SMALL__"); diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 10893324d3f..16e44855872 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -83,8 +83,8 @@ AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A, AARCH64_FL_FOR /* ARMv8.2-A Architecture Processors. */ /* ARM ('A') cores. */ -AARCH64_CORE("cortex-a55", cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC, cortexa53, 0x41, 0xd05, -1) -AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC, cortexa73, 0x41, 0xd0a, -1) +AARCH64_CORE("cortex-a55", cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa53, 0x41, 0xd05, -1) +AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, 0xd0a, -1) /* ARMv8-A big.LITTLE implementations. */ @@ -95,6 +95,6 @@ AARCH64_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, 8A, AARCH /* ARM DynamIQ big.LITTLE configurations. */ -AARCH64_CORE("cortex-a75.cortex-a55", cortexa75cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd0a, 0xd05), -1) +AARCH64_CORE("cortex-a75.cortex-a55", cortexa75cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd0a, 0xd05), -1) #undef AARCH64_CORE diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index a989a2ec23e..2c808f0b9ef 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -43,8 +43,8 @@ AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO | AARCH64_FL_F16, "fp") /* Enabling "simd" also enables "fp". - Disabling "simd" also disables "crypto". */ -AARCH64_OPT_EXTENSION("simd", AARCH64_FL_SIMD, AARCH64_FL_FP, AARCH64_FL_CRYPTO, "asimd") + Disabling "simd" also disables "crypto" and "dotprod". */ +AARCH64_OPT_EXTENSION("simd", AARCH64_FL_SIMD, AARCH64_FL_FP, AARCH64_FL_CRYPTO | AARCH64_FL_DOTPROD, "asimd") /* Enabling "crypto" also enables "fp", "simd". Disabling "crypto" just disables "crypto". */ @@ -67,4 +67,8 @@ AARCH64_OPT_EXTENSION("rcpc", AARCH64_FL_RCPC, 0, 0, "lrcpc") Disabling "rdma" just disables "rdma". */ AARCH64_OPT_EXTENSION("rdma", AARCH64_FL_RDMA, AARCH64_FL_FP | AARCH64_FL_SIMD, 0, "asimdrdm") +/* Enabling "dotprod" also enables "simd". + Disabling "dotprod" only disables "dotprod". */ +AARCH64_OPT_EXTENSION("dotprod", AARCH64_FL_DOTPROD, AARCH64_FL_SIMD, 0, "asimddp") + #undef AARCH64_OPT_EXTENSION diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 1c3aff587d2..98d93c69e23 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -136,14 +136,15 @@ extern unsigned aarch64_architecture_version; #define AARCH64_FL_CRC (1 << 3) /* Has CRC. */ /* ARMv8.1-A architecture extensions. */ #define AARCH64_FL_LSE (1 << 4) /* Has Large System Extensions. */ -#define AARCH64_FL_RDMA (1 << 5) /* Has Round Double Multiply Add. */ -#define AARCH64_FL_V8_1 (1 << 6) /* Has ARMv8.1-A extensions. */ +#define AARCH64_FL_RDMA (1 << 5) /* Has Round Double Multiply Add. */ +#define AARCH64_FL_V8_1 (1 << 6) /* Has ARMv8.1-A extensions. */ /* ARMv8.2-A architecture extensions. */ -#define AARCH64_FL_V8_2 (1 << 8) /* Has ARMv8.2-A features. */ +#define AARCH64_FL_V8_2 (1 << 8) /* Has ARMv8.2-A features. */ #define AARCH64_FL_F16 (1 << 9) /* Has ARMv8.2-A FP16 extensions. */ /* ARMv8.3-A architecture extensions. */ -#define AARCH64_FL_V8_3 (1 << 10) /* Has ARMv8.3-A features. */ -#define AARCH64_FL_RCPC (1 << 11) /* Has support for RCpc model. */ +#define AARCH64_FL_V8_3 (1 << 10) /* Has ARMv8.3-A features. */ +#define AARCH64_FL_RCPC (1 << 11) /* Has support for RCpc model. */ +#define AARCH64_FL_DOTPROD (1 << 12) /* Has ARMv8.2-A Dot Product ins. */ /* Has FP and SIMD. */ #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) @@ -172,6 +173,7 @@ extern unsigned aarch64_architecture_version; #define AARCH64_ISA_V8_2 (aarch64_isa_flags & AARCH64_FL_V8_2) #define AARCH64_ISA_F16 (aarch64_isa_flags & AARCH64_FL_F16) #define AARCH64_ISA_V8_3 (aarch64_isa_flags & AARCH64_FL_V8_3) +#define AARCH64_ISA_DOTPROD (aarch64_isa_flags & AARCH64_FL_DOTPROD) /* Crypto is an optional extension to AdvSIMD. */ #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO) @@ -186,6 +188,9 @@ extern unsigned aarch64_architecture_version; #define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16) #define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16) +/* Dot Product is an optional extension to AdvSIMD enabled through +dotprod. */ +#define TARGET_DOTPROD (TARGET_SIMD && AARCH64_ISA_DOTPROD) + /* ARMv8.3-A features. */ #define TARGET_ARMV8_3 (AARCH64_ISA_V8_3) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 4faeb457b19..b358e09b45d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -14382,6 +14382,8 @@ Enable FP16 extension. This also enables floating-point instructions. Enable the RcPc extension. This does not change code generation from GCC, but is passed on to the assembler, enabling inline asm statements to use instructions from the RcPc extension. +@item dotprod +Enable the Dot Product extension. This also enables Advanced SIMD instructions. @end table -- 2.30.2