From 1de77632e8096eeca02044a48b1a4b5144f0279b Mon Sep 17 00:00:00 2001 From: whitequark Date: Sun, 13 Oct 2019 03:39:56 +0000 Subject: [PATCH] hdl.ir: allow ClockSignal and ResetSignal in ports. Fixes #248. --- nmigen/hdl/ir.py | 1 + nmigen/hdl/xfrm.py | 4 ++-- nmigen/test/test_hdl_ir.py | 11 +++++++++++ 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/nmigen/hdl/ir.py b/nmigen/hdl/ir.py index 0f718ff..4232c52 100644 --- a/nmigen/hdl/ir.py +++ b/nmigen/hdl/ir.py @@ -540,6 +540,7 @@ class Fragment: if ports is None: fragment._propagate_ports(ports=(), all_undef_as_ports=True) else: + ports = map(DomainLowerer(fragment.domains).on_value, ports) new_ports = [] for cd in new_domains: new_ports.append(cd.clk) diff --git a/nmigen/hdl/xfrm.py b/nmigen/hdl/xfrm.py index 889e4b0..2d4e639 100644 --- a/nmigen/hdl/xfrm.py +++ b/nmigen/hdl/xfrm.py @@ -486,8 +486,8 @@ class DomainRenamer(FragmentTransformer, ValueTransformer, StatementTransformer) class DomainLowerer(FragmentTransformer, ValueTransformer, StatementTransformer): - def __init__(self): - self.domains = None + def __init__(self, domains=None): + self.domains = domains def _resolve(self, domain, context): if domain not in self.domains: diff --git a/nmigen/test/test_hdl_ir.py b/nmigen/test/test_hdl_ir.py index 82b9ed1..e51ae4e 100644 --- a/nmigen/test/test_hdl_ir.py +++ b/nmigen/test/test_hdl_ir.py @@ -264,6 +264,17 @@ class FragmentPortsTestCase(FHDLTestCase): (s, "io") ])) + def test_clk_rst(self): + sync = ClockDomain() + f = Fragment() + f.add_domains(sync) + + f = f.prepare(ports=(ClockSignal("sync"), ResetSignal("sync"))) + self.assertEqual(f.ports, SignalDict([ + (sync.clk, "i"), + (sync.rst, "i"), + ])) + class FragmentDomainsTestCase(FHDLTestCase): def test_iter_signals(self): -- 2.30.2