From 1dfc22c8fe1bfb3387195df4a0509bbd35c33678 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 25 Sep 2018 06:47:30 +0100 Subject: [PATCH] add decode.h header to sv.h --- riscv/sv.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/riscv/sv.h b/riscv/sv.h index 7b98c92..cd2f8fb 100644 --- a/riscv/sv.h +++ b/riscv/sv.h @@ -3,6 +3,8 @@ #ifndef _RISCV_SIMPLE_V_H #define _RISCV_SIMPLE_V_H +#include "decode.h" + // this table is for the CSRs (4? for RV32E, 16 for other types) // it's a CAM that's used to generate 2 tables (below) // just as in RV, writing to entries in this CAM *clears* -- 2.30.2