From 1e0e96f9a0ee552217bd54549d15e46a3fcffe06 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 28 Feb 2020 16:25:09 +0100 Subject: [PATCH] interconnect/axi: add AXI Stream definition and get_ios/connect_to_pads methods. --- litex/soc/interconnect/axi.py | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py index 7816315b..64d88ff3 100644 --- a/litex/soc/interconnect/axi.py +++ b/litex/soc/interconnect/axi.py @@ -138,6 +138,38 @@ class AXILiteInterface(Record): r.append(pad.eq(sig)) return r +# AXI Stream Definition ---------------------------------------------------------------------------- + +class AXIStreamInterface(stream.Endpoint): + def __init__(self, data_width=32): + self.data_width = data_width + stream.Endpoint.__init__(self, [("data", data_width)]) + + def get_ios(self, bus_name="axi"): + subsignals = [ + Subsignal("tvalid", Pins(1)), + Subsignal("tlast", Pins(1)), + Subsignal("tready", Pins(1)), + Subsignal("tdata", Pins(self.data_width)), + ] + ios = [(bus_name , 0) + tuple(subsignals)] + return ios + + def connect_to_pads(self, pads, mode="master"): + assert mode in ["slave", "master"] + r = [] + if mode == "master": + r.append(pads.tvalid.eq(self.valid)) + r.append(self.ready.eq(pads.tready)) + r.append(pads.tlast.eq(self.last)) + r.append(pads.tdata.eq(self.data)) + if mode == "slave": + r.append(self.valid.eq(pads.tvalid)) + r.append(pads.tready.eq(self.ready)) + r.append(self.last.eq(pads.tlast)) + r.append(self.data.eq(pads.tdata)) + return r + # AXI Bursts to Beats ------------------------------------------------------------------------------ class AXIBurst2Beat(Module): -- 2.30.2