From 1e1356b2ad2500e8aeefb8c3b64575ccac685eca Mon Sep 17 00:00:00 2001 From: =?utf8?q?Daniel=20Sch=C3=BCrmann?= Date: Fri, 15 Nov 2019 08:20:06 +0100 Subject: [PATCH] aco: implement 64bit i2b for SI /CI Reviewed-by: Rhys Perry --- src/amd/compiler/aco_instruction_selection.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 85ed7b3bf61..82b6989bb72 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -2115,8 +2115,13 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) Definition(dst), Operand(0u), src).def(0).setHint(vcc); } else { assert(src.regClass() == s1 || src.regClass() == s2); - Temp tmp = bld.sopc(src.size() == 2 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::s_cmp_lg_u32, - bld.scc(bld.def(s1)), Operand(0u), src); + Temp tmp; + if (src.regClass() == s2 && ctx->program->chip_class <= GFX7) { + tmp = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), Operand(0u), src).def(1).getTemp(); + } else { + tmp = bld.sopc(src.size() == 2 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::s_cmp_lg_u32, + bld.scc(bld.def(s1)), Operand(0u), src); + } bool_to_vector_condition(ctx, tmp, dst); } break; -- 2.30.2