From 1e5ddd3be4498155c1b64d951ff8ecdf435ffe7d Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Thu, 10 Oct 1996 19:08:46 +0000 Subject: [PATCH] * mn10300-opc.c (mn10300_opcodes): Fix destination register for shift-by-register opcodes. Bug found by testsuite. --- opcodes/ChangeLog | 3 +++ opcodes/mn10300-opc.c | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 5dc325bfa19..1420c9a6780 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,8 @@ Thu Oct 10 10:25:58 1996 Jeffrey A Law (law@cygnus.com) + * mn10300-opc.c (mn10300_opcodes): Fix destination register + for shift-by-register opcodes. + * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM into [AD][MN][01] for encoding the position of the register in the opcode. diff --git a/opcodes/mn10300-opc.c b/opcodes/mn10300-opc.c index f83edb2f2a9..b4fb5c78502 100644 --- a/opcodes/mn10300-opc.c +++ b/opcodes/mn10300-opc.c @@ -321,11 +321,11 @@ const struct mn10300_opcode mn10300_opcodes[] = { { "bclr", 0xfe010000, 0xffff0000, FMT_D5, {IMM8, MEM(ABS32)}}, { "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, {IMM8, MEM2(SD8N,AN0)}}, -{ "asr", 0xf2b0, 0xfff0, FMT_D0, {DM1, DN1}}, +{ "asr", 0xf2b0, 0xfff0, FMT_D0, {DM1, DN0}}, { "asr", 0xf8c800, 0xfffc00, FMT_D1, {IMM8, DN0}}, -{ "lsr", 0xf2a0, 0xfff0, FMT_D0, {DM1, DN1}}, +{ "lsr", 0xf2a0, 0xfff0, FMT_D0, {DM1, DN0}}, { "lsr", 0xf8c400, 0xfffc00, FMT_D1, {IMM8, DN0}}, -{ "asl", 0xf290, 0xfff0, FMT_D0, {DM1, DN1}}, +{ "asl", 0xf290, 0xfff0, FMT_D0, {DM1, DN0}}, { "asl", 0xf8c000, 0xfffc00, FMT_D1, {IMM8, DN0}}, { "asl2", 0x54, 0xfc, FMT_S0, {DN0}}, { "ror", 0xf284, 0xfffc, FMT_D0, {DN0}}, -- 2.30.2