From 1e69134caf6095dc09ecc692e7eda5045730ea7d Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 23 Mar 2020 13:46:19 +0000
Subject: [PATCH] split sim classes out into separate module

---
 src/soc/experiment/score6600.py | 77 +-----------------------------
 src/soc/experiment/sim.py       | 84 +++++++++++++++++++++++++++++++++
 2 files changed, 86 insertions(+), 75 deletions(-)
 create mode 100644 src/soc/experiment/sim.py

diff --git a/src/soc/experiment/score6600.py b/src/soc/experiment/score6600.py
index babce243..c98ac04a 100644
--- a/src/soc/experiment/score6600.py
+++ b/src/soc/experiment/score6600.py
@@ -25,19 +25,8 @@ from random import randint, seed
 from copy import deepcopy
 from math import log
 
-
-class MemSim:
-    def __init__(self, regwid, addrw):
-        self.regwid = regwid
-        self.ddepth = 1 # regwid//8
-        depth = (1<<addrw) // self.ddepth
-        self.mem = list(range(0, depth))
-
-    def ld(self, addr):
-        return self.mem[addr>>self.ddepth]
-
-    def st(self, addr, data):
-        self.mem[addr>>self.ddepth] = data & ((1<<self.regwid)-1)
+from soc.experiment.sim import RegSim, MemSim
+from soc.experiment.sim import IADD, ISUB, IMUL, ISHF, IBGT, IBLT, IBEQ, IBNE
 
 
 class CompUnitsBase(Elaboratable):
@@ -846,68 +835,6 @@ class IssueToScoreboard(Elaboratable):
         return list(self)
 
 
-IADD = 0
-ISUB = 1
-IMUL = 2
-ISHF = 3
-IBGT = 4
-IBLT = 5
-IBEQ = 6
-IBNE = 7
-
-
-class RegSim:
-    def __init__(self, rwidth, nregs):
-        self.rwidth = rwidth
-        self.regs = [0] * nregs
-
-    def op(self, op, op_imm, imm, src1, src2, dest):
-        maxbits = (1 << self.rwidth) - 1
-        src1 = self.regs[src1] & maxbits
-        if op_imm:
-            src2 = imm
-        else:
-            src2 = self.regs[src2] & maxbits
-        if op == IADD:
-            val = src1 + src2
-        elif op == ISUB:
-            val = src1 - src2
-        elif op == IMUL:
-            val = src1 * src2
-        elif op == ISHF:
-            val = src1 >> (src2 & maxbits)
-        elif op == IBGT:
-            val = int(src1 > src2)
-        elif op == IBLT:
-            val = int(src1 < src2)
-        elif op == IBEQ:
-            val = int(src1 == src2)
-        elif op == IBNE:
-            val = int(src1 != src2)
-        else:
-            return 0 # LD/ST TODO
-        val &= maxbits
-        self.setval(dest, val)
-        return val
-
-    def setval(self, dest, val):
-        print ("sim setval", dest, hex(val))
-        self.regs[dest] = val
-
-    def dump(self, dut):
-        for i, val in enumerate(self.regs):
-            reg = yield dut.intregs.regs[i].reg
-            okstr = "OK" if reg == val else "!ok"
-            print("reg %d expected %x received %x %s" % (i, val, reg, okstr))
-
-    def check(self, dut):
-        for i, val in enumerate(self.regs):
-            reg = yield dut.intregs.regs[i].reg
-            if reg != val:
-                print("reg %d expected %x received %x\n" % (i, val, reg))
-                yield from self.dump(dut)
-                assert False
-
 def instr_q(dut, op, op_imm, imm, src1, src2, dest,
             branch_success, branch_fail):
     instrs = [{'oper_i': op, 'dest_i': dest, 'imm_i': imm, 'opim_i': op_imm,
diff --git a/src/soc/experiment/sim.py b/src/soc/experiment/sim.py
new file mode 100644
index 00000000..d24b013d
--- /dev/null
+++ b/src/soc/experiment/sim.py
@@ -0,0 +1,84 @@
+from soc.decoder.power_enums import InternalOp
+
+from random import randint, seed
+from copy import deepcopy
+from math import log
+
+
+class MemSim:
+    def __init__(self, regwid, addrw):
+        self.regwid = regwid
+        self.ddepth = 1 # regwid//8
+        depth = (1<<addrw) // self.ddepth
+        self.mem = list(range(0, depth))
+
+    def ld(self, addr):
+        return self.mem[addr>>self.ddepth]
+
+    def st(self, addr, data):
+        self.mem[addr>>self.ddepth] = data & ((1<<self.regwid)-1)
+
+
+
+IADD = 0
+ISUB = 1
+IMUL = 2
+ISHF = 3
+IBGT = 4
+IBLT = 5
+IBEQ = 6
+IBNE = 7
+
+
+class RegSim:
+    def __init__(self, rwidth, nregs):
+        self.rwidth = rwidth
+        self.regs = [0] * nregs
+
+    def op(self, op, op_imm, imm, src1, src2, dest):
+        maxbits = (1 << self.rwidth) - 1
+        src1 = self.regs[src1] & maxbits
+        if op_imm:
+            src2 = imm
+        else:
+            src2 = self.regs[src2] & maxbits
+        if op == IADD:
+            val = src1 + src2
+        elif op == ISUB:
+            val = src1 - src2
+        elif op == IMUL:
+            val = src1 * src2
+        elif op == ISHF:
+            val = src1 >> (src2 & maxbits)
+        elif op == IBGT:
+            val = int(src1 > src2)
+        elif op == IBLT:
+            val = int(src1 < src2)
+        elif op == IBEQ:
+            val = int(src1 == src2)
+        elif op == IBNE:
+            val = int(src1 != src2)
+        else:
+            return 0 # LD/ST TODO
+        val &= maxbits
+        self.setval(dest, val)
+        return val
+
+    def setval(self, dest, val):
+        print ("sim setval", dest, hex(val))
+        self.regs[dest] = val
+
+    def dump(self, dut):
+        for i, val in enumerate(self.regs):
+            reg = yield dut.intregs.regs[i].reg
+            okstr = "OK" if reg == val else "!ok"
+            print("reg %d expected %x received %x %s" % (i, val, reg, okstr))
+
+    def check(self, dut):
+        for i, val in enumerate(self.regs):
+            reg = yield dut.intregs.regs[i].reg
+            if reg != val:
+                print("reg %d expected %x received %x\n" % (i, val, reg))
+                yield from self.dump(dut)
+                assert False
+
-- 
2.30.2