From 1e7783a41e0a6639094967432e5c34d1ddc9e17a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 12 Mar 2013 16:13:20 +0100 Subject: [PATCH] build.py: use implicit get_fragment --- build.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build.py b/build.py index 81539374..ef125678 100755 --- a/build.py +++ b/build.py @@ -58,7 +58,7 @@ NET "asfifo*/preset_empty*" TIG; "jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v") plat.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v") - plat.build_cmdline(soc.get_fragment(), clock_domains=soc.crg.get_clock_domains()) + plat.build_cmdline(soc, clock_domains=soc.crg.get_clock_domains()) if __name__ == "__main__": main() -- 2.30.2