From 1e80128dcaa4a79d03215d5f6864d644455b4684 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 1 Aug 2018 09:49:13 +0100 Subject: [PATCH] AddingPeripherals.mdwn --- docs/AddingPeripherals.mdwn | 20 ++++++++++++++++++++ src/bsv/peripheral_gen/sdram.py | 5 +++-- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/docs/AddingPeripherals.mdwn b/docs/AddingPeripherals.mdwn index 964bc8c..ae00d55 100644 --- a/docs/AddingPeripherals.mdwn +++ b/docs/AddingPeripherals.mdwn @@ -415,3 +415,23 @@ Re-run the tool and check that the correct-looking code has been created: fb0 <- mkAXI4_Slave_to_FlexBus_Master_Xactor; Ifc_rgbttl_dummy lcd0 <- mkrgbttl_dummy(); +The next thing to do: searching for the string "sdram\_out" shows that the +original hand-generated code contains (contained) a declaration of the +SDRAM Interface, presumably to which, when compiling to run on an FPGA, +the SDRAM interface would be connected at the top level. Through this +interface, connections would be done *by hand* to the IO pads, whereas +now they are to be connected *automatically* (on the peripheral side) +to the IO pads in the pinmux. However, at the time of writing this is +not fully understood by the author, so the fastifdecl and extfastifinstance +functions are modified to generate the correct output but the code is +*commented out*: + + def extfastifinstance(self, name, count): + return "// TODO" + self._extifinstance(name, count, "_out", "", True, + ".if_sdram_out") + + def fastifdecl(self, name, count): + return "// (*always_ready*) interface " + \ + "Ifc_sdram_out sdr{0}_out;".format(count) + + diff --git a/src/bsv/peripheral_gen/sdram.py b/src/bsv/peripheral_gen/sdram.py index cc6c0bd..9cdf1fd 100644 --- a/src/bsv/peripheral_gen/sdram.py +++ b/src/bsv/peripheral_gen/sdram.py @@ -11,10 +11,11 @@ class sdram(PBase): def extfastifinstance(self, name, count): return "// TODO" + self._extifinstance(name, count, "_out", "", True, - ".sdram_side") + ".if_sdram_out") def fastifdecl(self, name, count): - return "//interface FlexBus_Master_IFC sdr{0}_out;".format(count) + return "// (*always_ready*) interface " + \ + "Ifc_sdram_out sdr{0}_out;".format(count) def get_clock_reset(self, name, count): return "slow_clock, slow_reset" -- 2.30.2