From 1e87df618f6f507830d0b37ba1d6f6f7a26d2943 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 13 Feb 2022 17:34:13 +0000 Subject: [PATCH] add lut2 ilang output to lut.py to help testing --- src/nmutil/lut.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/nmutil/lut.py b/src/nmutil/lut.py index 7ad9018..d9aeb36 100644 --- a/src/nmutil/lut.py +++ b/src/nmutil/lut.py @@ -15,6 +15,7 @@ https://www.felixcloutier.com/x86/vpternlogd:vpternlogq from nmigen.hdl.ast import Array, Cat, Repl, Signal from nmigen.hdl.dsl import Module from nmigen.hdl.ir import Elaboratable +from nmigen.cli import rtlil from dataclasses import dataclass @@ -184,3 +185,9 @@ class TreeBitwiseLut(Elaboratable): # useful to see what is going on: # python3 src/nmutil/test/test_lut.py # yosys <<<"read_ilang sim_test_out/__main__.TestBitwiseLut.test_tree/0.il; proc;;; show top" + +if __name__ == '__main__': + dut = BitwiseLut(2, 64) + vl = rtlil.convert(dut, ports=dut.ports()) + with open("test_lut2.il", "w") as f: + f.write(vl) -- 2.30.2