From 1e8e1b0bf46bf2f98648e3a6f6fb2d8f11bbcf4f Mon Sep 17 00:00:00 2001 From: whitequark Date: Mon, 23 Sep 2019 20:15:29 +0000 Subject: [PATCH] vendor.xilinx_7series: override reset synchronizer. --- nmigen/vendor/xilinx_7series.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py index b25c4e9..e3ea1fa 100644 --- a/nmigen/vendor/xilinx_7series.py +++ b/nmigen/vendor/xilinx_7series.py @@ -371,3 +371,18 @@ class Xilinx7SeriesPlatform(TemplatedPlatform): m.d[ff_sync._o_domain] += o.eq(i) m.d.comb += ff_sync.o.eq(flops[-1]) return m + + def get_reset_sync(self, reset_sync): + m = Module() + m.domains += ClockDomain("reset_sync", async_reset=True, local=True) + flops = [Signal(1, name="stage{}".format(index), reset=1, + attrs={"ASYNC_REG": "TRUE"}) + for index in range(reset_sync._stages)] + for i, o in zip((0, *flops), flops): + m.d.reset_sync += o.eq(i) + m.d.comb += [ + ClockSignal("reset_sync").eq(ClockSignal(reset_sync._domain)), + ResetSignal("reset_sync").eq(reset_sync.arst), + ResetSignal(reset_sync._domain).eq(flops[-1]) + ] + return m -- 2.30.2