From 1ea9206ac52cffd3f77af12805216a4b435ebaa4 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Sun, 27 Mar 2011 09:33:20 +0000 Subject: [PATCH] re PR target/38598 (MIPS extendsidi2 does not have a LO alternative) gcc/ PR target/38598 * config/mips/mips.md (extendsidi2): Add an "l" alternative. Update commentary. gcc/testsuite/ PR target/38598 * gcc.target/mips/madd-7.c: Remove -mlong32. * gcc.target/mips/msub-7.c: Likewise. From-SVN: r171572 --- gcc/ChangeLog | 6 ++++++ gcc/config/mips/mips.md | 28 ++++++++++++++++---------- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.target/mips/madd-7.c | 3 +-- gcc/testsuite/gcc.target/mips/msub-7.c | 3 +-- 5 files changed, 31 insertions(+), 15 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c80e4ee2c57..41c0ef22801 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2011-03-27 Richard Sandiford + + PR target/38598 + * config/mips/mips.md (extendsidi2): Add an "l" alternative. + Update commentary. + 2011-03-27 Richard Sandiford * config/mips/mips.c (mips_prepare_builtin_arg): Replace icode and diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index bb871036327..c5276c0dcfa 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -2963,19 +2963,25 @@ ;; Extension insns. ;; Those for integer source operand are ordered widest source type first. -;; When TARGET_64BIT, all SImode integer registers should already be in -;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can -;; therefore get rid of register->register instructions if we constrain -;; the source to be in the same register as the destination. -;; -;; The register alternative has type "arith" so that the pre-reload -;; scheduler will treat it as a move. This reflects what happens if -;; the register alternative needs a reload. +;; When TARGET_64BIT, all SImode integer and accumulator registers +;; should already be in sign-extended form (see TRULY_NOOP_TRUNCATION +;; and truncdisi2). We can therefore get rid of register->register +;; instructions if we constrain the source to be in the same register as +;; the destination. +;; +;; Only the pre-reload scheduler sees the type of the register alternatives; +;; we split them into nothing before the post-reload scheduler runs. +;; These alternatives therefore have type "move" in order to reflect +;; what happens if the two pre-reload operands cannot be tied, and are +;; instead allocated two separate GPRs. We don't distinguish between +;; the GPR and LO cases because we don't usually know during pre-reload +;; scheduling whether an operand will be LO or not. (define_insn_and_split "extendsidi2" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))] + [(set (match_operand:DI 0 "register_operand" "=d,l,d") + (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,0,m")))] "TARGET_64BIT" "@ + # # lw\t%0,%1" "&& reload_completed && register_operand (operands[1], VOIDmode)" @@ -2984,7 +2990,7 @@ emit_note (NOTE_INSN_DELETED); DONE; } - [(set_attr "move_type" "move,load") + [(set_attr "move_type" "move,move,load") (set_attr "mode" "DI")]) (define_expand "extend2" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index df0ab831bc8..781db97ffd6 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2011-03-27 Richard Sandiford + + PR target/38598 + * gcc.target/mips/madd-7.c: Remove -mlong32. + * gcc.target/mips/msub-7.c: Likewise. + 2011-03-27 Ira Rosen * gcc.dg/vect/vect-outer-5.c: Reduce the distance between data diff --git a/gcc/testsuite/gcc.target/mips/madd-7.c b/gcc/testsuite/gcc.target/mips/madd-7.c index 93ed0fc6f06..b43d7207427 100644 --- a/gcc/testsuite/gcc.target/mips/madd-7.c +++ b/gcc/testsuite/gcc.target/mips/madd-7.c @@ -1,5 +1,4 @@ -/* -mlong32 added because of PR target/38598. */ -/* { dg-options "-O2 -march=5kc -mlong32" } */ +/* { dg-options "-O2 -march=5kc" } */ /* { dg-final { scan-assembler-not "\tmul\t" } } */ /* { dg-final { scan-assembler "\tmadd\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/msub-7.c b/gcc/testsuite/gcc.target/mips/msub-7.c index ca90cee9ea5..7ae96acb42e 100644 --- a/gcc/testsuite/gcc.target/mips/msub-7.c +++ b/gcc/testsuite/gcc.target/mips/msub-7.c @@ -1,5 +1,4 @@ -/* -mlong32 added because of PR target/38598. */ -/* { dg-options "-O2 -march=5kc -mlong32" } */ +/* { dg-options "-O2 -march=5kc" } */ /* { dg-final { scan-assembler-not "\tmul\t" } } */ /* { dg-final { scan-assembler "\tmsub\t" } } */ -- 2.30.2