From 1ed0782f7a5fb53d0a162ebe1fe337b5a18c9293 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Tue, 16 Nov 2021 19:22:53 +0100 Subject: [PATCH] pi_ld busy waiting fix --- src/soc/config/test/test_pi2ls.py | 2 +- src/soc/experiment/test/test_loadstore1.py | 16 +++++++++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/src/soc/config/test/test_pi2ls.py b/src/soc/config/test/test_pi2ls.py index eea65326..c8a4b39a 100644 --- a/src/soc/config/test/test_pi2ls.py +++ b/src/soc/config/test/test_pi2ls.py @@ -99,7 +99,7 @@ def pi_ld(port1, addr, datalen, msr_pr=0): if exc_happened: return 0 - yield from wait_busy(port1, no=False) # wait while not busy + yield from wait_busy(port1, no=True) # wait while busy return data diff --git a/src/soc/experiment/test/test_loadstore1.py b/src/soc/experiment/test/test_loadstore1.py index cf347059..3c4013d1 100644 --- a/src/soc/experiment/test/test_loadstore1.py +++ b/src/soc/experiment/test/test_loadstore1.py @@ -7,7 +7,7 @@ from random import randint, seed from nmigen.sim import Simulator, Delay, Settle from nmutil.util import wrap -from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst +from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst, wait_busy from soc.config.test.test_loadstore import TestMemPspec from soc.config.loadstore import ConfigMemoryPortInterface @@ -137,8 +137,22 @@ def _test_loadstore1(dut, mem): assert(happened==1) assert(alignment==1) assert(dar==addr) + yield from wait_busy(pi, no=True) # wait while busy + # wait is only needed in case of in exception here print("=== alignment error test passed ===") + """ + #next test + addr = 0xFF100e000 + ld_data = yield from pi_ld_debug(pi, addr, 8, msr_pr=1) + alignment = yield pi.exc_o.alignment + happened = yield pi.exc_o.happened + dar = yield pi.dar_o + assert(happened==1) + assert(alignment==1) + assert(dar==addr) + """ + yield stop = True -- 2.30.2