From 1edae9cfbf7d9850ad5c614795d2946d86cc8440 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 25 Dec 2020 01:42:27 +0000 Subject: [PATCH] --- openpower/sv/overview.mdwn | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index b7edc6313..98371c226 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -101,7 +101,11 @@ A particularly interesting case is if the destination is scalar, and the first f If all three registers are marked as Vector then the "traditional" predicated Vector behaviour is provided. Yet, just as before, all other options are still provided, right the way back to the pure-scalar case, as if this were a straight OpenPOWER v3.0B non-augmented instruction. -Predication therefore provides several modes traditionally seen in Vector ISAs, particularly if the predicate may be set conveniently as a single bit: this gives VINSERT (VINDEX) behaviour. VSPLAT (result broadcasting) is provided by making the sources scalar and the destination a vector. VSELECT is provided by setting up (at least one of) the sources as a vector, using a single bit in olthe predicate, and the destination as a scalar. +Single Predication therefore provides several modes traditionally seen in Vector ISAs: + +* the predicate may be set as a single bit, the sources are scalar and the destination a vector: this gives VINSERT (VINDEX) behaviour. +* VSPLAT (result broadcasting) is provided by making the sources scalar and the destination a vector. +* VSELECT is provided by setting up (at least one of) the sources as a vector, using a single bit in olthe predicate, and the destination as a scalar. # Predicate "zeroing" mode -- 2.30.2