From 1ede39bca3a3f568fe33219aa5042718cf4d0cf4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 2 Jun 2020 19:26:11 +0100 Subject: [PATCH] add comment about fast1 and fast2 in branch test_pipe_caller --- libreriscv | 2 +- src/soc/fu/branch/test/test_pipe_caller.py | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/libreriscv b/libreriscv index 6b08375a..041f868b 160000 --- a/libreriscv +++ b/libreriscv @@ -1 +1 @@ -Subproject commit 6b08375a1f5a0f3575fe86f7379506da4c4d9b90 +Subproject commit 041f868b620685068f375bce39c3aacf6aa986c4 diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py index 0028fb41..dddfc4d1 100644 --- a/src/soc/fu/branch/test/test_pipe_caller.py +++ b/src/soc/fu/branch/test/test_pipe_caller.py @@ -215,6 +215,8 @@ class TestRunner(FHDLTestCase): yield branch.p.data_i.spr1.eq(sim.spr['CTR'].value) print(f"cr0: {sim.crl[0].get_range()}") + # TODO: this needs to now be read_fast1.data and read_fast2.data + spr2_en = yield dec2.e.read_spr2.ok if spr2_en: spr2_sel = yield dec2.e.read_spr2.data -- 2.30.2