From 1ee3e45b8e7000f81822340cf45ffb3085305438 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 9 Jun 2020 12:08:32 +0100 Subject: [PATCH] add truncaddr function to L0CacheBuffer test class --- src/soc/experiment/l0_cache.py | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index 1a941a47..39bf51ed 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -162,8 +162,8 @@ class DataMergerRecord(Record): #FIXME: make resetless -# TODO: formal verification +# TODO: formal verification class DataMerger(Elaboratable): """DataMerger @@ -306,11 +306,19 @@ class L0CacheBuffer(Elaboratable): def __init__(self, n_units, mem, regwid=64, addrwid=48): self.n_units = n_units self.mem = mem + self.regwid = regwid + self.addrwid = addrwid ul = [] for i in range(n_units): ul.append(LDSTPort(i, regwid, addrwid)) self.dports = Array(ul) + def truncaddr(self, addr): + """truncates the address to the top bits of the memory granularity + """ + nbits = log2_int(self.mem.regwid) + return addr[nbits:] + def elaborate(self, platform): m = Module() comb, sync = m.d.comb, m.d.sync @@ -545,6 +553,7 @@ def l0_cache_ldst(dut): assert data == result, "data %x != %x" % (result, data) assert data2 == result2, "data2 %x != %x" % (result2, data2) + def data_merger_merge(dut): print("data_merger") #starting with all inputs zero @@ -567,6 +576,7 @@ def data_merger_merge(dut): assert en == 0xff yield + def test_l0_cache(): dut = TstL0CacheBuffer(regwid=64) -- 2.30.2