From 1ef9ad3f2a1387cb293e0380edec272bc3d97b07 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 28 Feb 2021 23:06:04 +0000
Subject: [PATCH]

---
 openpower/sv/implementation.mdwn | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 011a3e9fb..1ea5c8a91 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -77,6 +77,8 @@ An autogenerator containing CSV files is available so that the task of creating
 * python-based assembler-translator: 40% done (lkcl)
 * c++ macros: underway (jacob)
 
+Note when decoding the RM intobits different modes that LDST interprets the 5 mode bits differently not just on whether it is LD/ST bit also what *type* of LD/ST. Immediate LD/ST is further qualified to indicate if it operates in element-strided or unit-strided mode.  However Indexed LD/ST is not.
+
 Links:
 
 * <https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv_analysis.py;hb=HEAD>
-- 
2.30.2