From 1f0393b6c1a462f007f5b65c4d3aef134b32fd72 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 15 Sep 2022 13:16:25 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001.mdwn | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index dad82b579..b68822561 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -710,23 +710,29 @@ of this RFC. **legal, scalar and vector** -| width | assembler | prefix (if any) | suffix | description | -|-------|-----------|-----------------|-----------|---------------| -| 32bit | fishmv | none | 0x12345678| scalar EXT0nn | -| 64bit | sv.fishmv | 0x27000000 | 0x12345678| vector SVP64:EXT2nn | +| width | assembler | prefix? | suffix | description | +|-------|-----------|--------------|-----------|---------------| +| 32bit | fishmv | none | 0x12345678| scalar EXT0nn | +| 64bit | ss.fishmv | 0x26!zero | 0x12345678| scalar SVP64Single:EXT0nn | +| 64bit | sv.fishmv | 0x27nnnnnn | 0x12345678| vector SVP64:EXT0nn | OR: -| width | assembler | prefix (if any) | suffix | description | -|-------|-----------|-----------------|-----------|---------------| -| 64bit | fishmv | 0x24000000 | 0x12345678| scalar EXT2nn | -| 64bit | sv.fishmv | 0x26000000 | 0x12345678| vector SVP64:EXT0nn | - -* 32bit fishmv EXT0nn 0x12345678 or - 64bit scalar EXT2nn 0x240000000 0x12345678 (typo removed) -* vector fishmv 0x27nnnnnn 0x12345678 - -here the encodings are the same, 0x12345678 means the same thing in both cases. (and SVP64Single, wherever it is, whenever it is). +| width | assembler | prefix? | suffix | description | +|-------|-----------|--------------|-----------|---------------| +| 64bit | fishmv | 0x24000000 | 0x12345678| scalar EXT2nn | +| 64bit | ss.fishmv | 0x24!zero | 0x12345678| scalar SVP64Single:EXT2nn | +| 64bit | sv.fishmv | 0x26nnnnnn | 0x12345678| vector SVP64:EXT2nn | + +Here the encodings are the same, 0x12345678 means the same thing in +all cases. Anything other than this risks either damage (truncation +of capabilities of Simple-V) or far greater complexity in the +Decode Phase. + +A *potential* compromise is to reserve certain EXT2nn POs right +across the board +(in the Scalar Suffix side, irrespective of Prefix), some allocated +to Simple-V, some not. example, legal (sort-of) (edit, typo corrected) -- 2.30.2