From 1f1decd765cc184ee84baff709b216a2a387c3ae Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Mon, 8 Feb 2021 17:24:55 -0800 Subject: [PATCH] cpu,mem: Converting stats to supported units There are several stats having unit being a multiple of supported units. This change makes the following conversions: * MiB/s -> bytes/s * percentage -> ratio Change-Id: I9832796e87698daa7f87f91fa39ce40bbf92e737 Signed-off-by: Hoa Nguyen Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41013 Tested-by: kokoro Reviewed-by: Daniel Carvalho Reviewed-by: Bobby R. Bruce Maintainer: Bobby R. Bruce --- src/cpu/o3/fetch_impl.hh | 4 ++-- src/cpu/pred/bpred_unit.cc | 5 ++--- src/cpu/pred/bpred_unit.hh | 4 ++-- src/mem/mem_ctrl.cc | 12 ++++++------ src/mem/xbar.cc | 4 ++-- 5 files changed, 14 insertions(+), 15 deletions(-) diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 23ab06bc4..24e746433 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -193,8 +193,8 @@ FetchStatGroup::FetchStatGroup(O3CPU *cpu, DefaultFetch *fetch) "Number of outstanding ITLB misses that were squashed"), ADD_STAT(nisnDist, "Number of instructions fetched each cycle (Total)"), - ADD_STAT(idleRate, "Percent of cycles fetch was idle", - idleCycles * 100 / cpu->baseStats.numCycles), + ADD_STAT(idleRate, "Ratio of cycles fetch was idle", + idleCycles / cpu->baseStats.numCycles), ADD_STAT(branchRate, "Number of branch fetches per cycle", branches / cpu->baseStats.numCycles), ADD_STAT(rate, "Number of inst fetches per cycle", diff --git a/src/cpu/pred/bpred_unit.cc b/src/cpu/pred/bpred_unit.cc index e618fb519..d32d75b22 100644 --- a/src/cpu/pred/bpred_unit.cc +++ b/src/cpu/pred/bpred_unit.cc @@ -74,8 +74,7 @@ BPredUnit::BPredUnitStats::BPredUnitStats(Stats::Group *parent) ADD_STAT(condIncorrect, "Number of conditional branches incorrect"), ADD_STAT(BTBLookups, "Number of BTB lookups"), ADD_STAT(BTBHits, "Number of BTB hits"), - ADD_STAT(BTBHitPct, "BTB Hit Percentage", - (BTBHits / BTBLookups) * 100), + ADD_STAT(BTBHitRatio, "BTB Hit Ratio", BTBHits / BTBLookups), ADD_STAT(RASUsed, "Number of times the RAS was used to get a target."), ADD_STAT(RASIncorrect, "Number of incorrect RAS predictions."), ADD_STAT(indirectLookups, "Number of indirect predictor lookups."), @@ -84,7 +83,7 @@ BPredUnit::BPredUnitStats::BPredUnitStats(Stats::Group *parent) ADD_STAT(indirectMispredicted, "Number of mispredicted indirect" " branches.") { - BTBHitPct.precision(6); + BTBHitRatio.precision(6); } ProbePoints::PMUUPtr diff --git a/src/cpu/pred/bpred_unit.hh b/src/cpu/pred/bpred_unit.hh index e445a39e7..ca164fa29 100644 --- a/src/cpu/pred/bpred_unit.hh +++ b/src/cpu/pred/bpred_unit.hh @@ -290,8 +290,8 @@ class BPredUnit : public SimObject Stats::Scalar BTBLookups; /** Stat for number of BTB hits. */ Stats::Scalar BTBHits; - /** Stat for percent times an entry in BTB found. */ - Stats::Formula BTBHitPct; + /** Stat for the ratio between BTB hits and BTB lookups. */ + Stats::Formula BTBHitRatio; /** Stat for number of times the RAS is used to get a target. */ Stats::Scalar RASUsed; /** Stat for number of times the RAS is incorrect. */ diff --git a/src/mem/mem_ctrl.cc b/src/mem/mem_ctrl.cc index c66d2381b..717e96664 100644 --- a/src/mem/mem_ctrl.cc +++ b/src/mem/mem_ctrl.cc @@ -1224,8 +1224,8 @@ MemCtrl::CtrlStats::CtrlStats(MemCtrl &_ctrl) ADD_STAT(bytesWrittenSys, "Total written bytes from the system interface side"), - ADD_STAT(avgRdBWSys, "Average system read bandwidth in MiByte/s"), - ADD_STAT(avgWrBWSys, "Average system write bandwidth in MiByte/s"), + ADD_STAT(avgRdBWSys, "Average system read bandwidth in Byte/s"), + ADD_STAT(avgWrBWSys, "Average system write bandwidth in Byte/s"), ADD_STAT(totGap, "Total gap between requests"), ADD_STAT(avgGap, "Average gap between requests"), @@ -1276,8 +1276,8 @@ MemCtrl::CtrlStats::regStats() .init(ctrl.writeBufferSize) .flags(nozero); - avgRdBWSys.precision(2); - avgWrBWSys.precision(2); + avgRdBWSys.precision(8); + avgWrBWSys.precision(8); avgGap.precision(2); // per-requestor bytes read and written to memory @@ -1337,8 +1337,8 @@ MemCtrl::CtrlStats::regStats() } // Formula stats - avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; - avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; + avgRdBWSys = (bytesReadSys) / simSeconds; + avgWrBWSys = (bytesWrittenSys) / simSeconds; avgGap = totGap / (readReqs + writeReqs); diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc index 7423374f4..6bf4baff0 100644 --- a/src/mem/xbar.cc +++ b/src/mem/xbar.cc @@ -141,7 +141,7 @@ BaseXBar::Layer::Layer(DstType& _port, BaseXBar& _xbar, port(_port), xbar(_xbar), _name(xbar.name() + "." + _name), state(IDLE), waitingForPeer(NULL), releaseEvent([this]{ releaseLayer(); }, name()), ADD_STAT(occupancy, "Layer occupancy (ticks)"), - ADD_STAT(utilization, "Layer utilization (%)") + ADD_STAT(utilization, "Layer utilization") { occupancy .flags(Stats::nozero); @@ -150,7 +150,7 @@ BaseXBar::Layer::Layer(DstType& _port, BaseXBar& _xbar, .precision(1) .flags(Stats::nozero); - utilization = 100 * occupancy / simTicks; + utilization = occupancy / simTicks; } template -- 2.30.2