From 1f33abd75db99567376f41a9f21cbf509167aa97 Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Thu, 13 Apr 2017 23:13:19 -0600 Subject: [PATCH] mips.mips.md (zero_extendsidi2): Do not allow SP to appear in operands[1] if it is a MEM and TARGET_MIPS16 is active. * config/mips.mips.md (zero_extendsidi2): Do not allow SP to appear in operands[1] if it is a MEM and TARGET_MIPS16 is active. (zero_extendsidi2_dext): Likewise. From-SVN: r246924 --- gcc/ChangeLog | 6 ++++++ gcc/config/mips/mips.md | 10 ++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 33b094e56f5..788f02942cc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-04-13 Jeff Law + + * config/mips.mips.md (zero_extendsidi2): Do not allow SP to appear + in operands[1] if it is a MEM and TARGET_MIPS16 is active. + (zero_extendsidi2_dext): Likewise. + 2017-04-13 Jakub Jelinek PR sanitizer/80403 diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 7acf00d0451..dd5e1e77436 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -3493,7 +3493,10 @@ (define_insn_and_split "*zero_extendsidi2" [(set (match_operand:DI 0 "register_operand" "=d,d") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))] - "TARGET_64BIT && !ISA_HAS_EXT_INS" + "TARGET_64BIT && !ISA_HAS_EXT_INS + && !(TARGET_MIPS16 + && MEM_P (operands[1]) + && reg_mentioned_p (stack_pointer_rtx, operands[1]))" "@ # lwu\t%0,%1" @@ -3509,7 +3512,10 @@ (define_insn "*zero_extendsidi2_dext" [(set (match_operand:DI 0 "register_operand" "=d,d") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))] - "TARGET_64BIT && ISA_HAS_EXT_INS" + "TARGET_64BIT && ISA_HAS_EXT_INS + && !(TARGET_MIPS16 + && MEM_P (operands[1]) + && reg_mentioned_p (stack_pointer_rtx, operands[1]))" "@ dext\t%0,%1,0,32 lwu\t%0,%1" -- 2.30.2