From 1f3c941a7875013f62e741bcf6f5795b081cff4f Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 4 Jul 2013 19:22:59 +0200 Subject: [PATCH] platforms/m1: move generic platform commands to do_finalize --- mibuild/platforms/m1.py | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py index ae391e76..80d61a14 100644 --- a/mibuild/platforms/m1.py +++ b/mibuild/platforms/m1.py @@ -120,3 +120,36 @@ class Platform(XilinxISEPlatform): def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io, lambda p: CRG_SE(p, "clk50", "user_btn", 20.0)) + + def do_finalize(self, fragment): + try: + self.add_platform_command(""" +NET "{clk50}" TNM_NET = "GRPclk50"; +TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%; +""", clk50=self.lookup_request("clk50")) + except ConstraintError: + pass + + try: + eth_clocks = self.lookup_request("eth_clocks") + self.add_platform_command(""" +NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk"; +NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk"; +TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%; +TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%; +TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns; +TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns; +""", phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx) + except ConstraintError: + pass + + for i in range(2): + si = "dviclk"+str(i) + try: + self.add_platform_command(""" +NET "{dviclk}" TNM_NET = "GRP"""+si+""""; +NET "{dviclk}" CLOCK_DEDICATED_ROUTE = FALSE; +TIMESPEC "TS"""+si+"""" = PERIOD "GRP"""+si+"""" 26.7 ns HIGH 50%; +""", dviclk=self.lookup_request("dvi_in", i).clk) + except ConstraintError: + pass -- 2.30.2