From 1f48e56d098e957e5ed2e40cdd21ad8262679993 Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Mon, 30 Jun 2003 09:57:58 +0200 Subject: [PATCH] i386.c (standard_80387_constant_p): Accept TFmode constants too. * i386.c (standard_80387_constant_p): Accept TFmode constants too. (init_ext_80387_constants): Likewise. (standard_80387_constant_rtx): Likewise. * i386.md (atanxf): Disable for TARGET_128BIT_LONG_LONG (atantf): Disable for !TARGET_128BIT_LONG_LONG (fyl2x_sfxf3, fyl2x_dfxf3): Accept TFmode operands. (fyl2x_xfxf3, fyl2x_tfxf3): Enable/disable as needed. (fscale_sfxf3, fscale_dfxf3): Accept TFmode operands. (fscale_xfxf3, fscale_tfxf3): Enable/disable as needed. (frndinttf2): New. (f2xm1tf2): New. (exp?f2): Use expsf2_tf when needed. (exp?f2_tf): New. (exptf): New. From-SVN: r68693 --- gcc/ChangeLog | 17 ++++ gcc/config/i386/i386.c | 8 +- gcc/config/i386/i386.md | 172 ++++++++++++++++++++++++++++++++++------ 3 files changed, 168 insertions(+), 29 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5c0039dfddd..fafbdb97b7b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,20 @@ +Mon Jun 30 09:52:39 CEST 2003 Jan Hubicka + + * i386.c (standard_80387_constant_p): Accept TFmode constants too. + (init_ext_80387_constants): Likewise. + (standard_80387_constant_rtx): Likewise. + * i386.md (atanxf): Disable for TARGET_128BIT_LONG_LONG + (atantf): Disable for !TARGET_128BIT_LONG_LONG + (fyl2x_sfxf3, fyl2x_dfxf3): Accept TFmode operands. + (fyl2x_xfxf3, fyl2x_tfxf3): Enable/disable as needed. + (fscale_sfxf3, fscale_dfxf3): Accept TFmode operands. + (fscale_xfxf3, fscale_tfxf3): Enable/disable as needed. + (frndinttf2): New. + (f2xm1tf2): New. + (exp?f2): Use expsf2_tf when needed. + (exp?f2_tf): New. + (exptf): New. + 2003-06-29 Uwe Stieber * config.gcc (sh*-*-kaos*): Put tm_file setting in separate case diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 8d9c08f99fa..9e9a8e6b976 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -4292,7 +4292,8 @@ init_ext_80387_constants () { real_from_string (&ext_80387_constants_table[i], cst[i]); /* Ensure each constant is rounded to XFmode precision. */ - real_convert (&ext_80387_constants_table[i], XFmode, + real_convert (&ext_80387_constants_table[i], + TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode, &ext_80387_constants_table[i]); } @@ -4316,7 +4317,7 @@ standard_80387_constant_p (x) /* For XFmode constants, try to find a special 80387 instruction on those CPUs that benefit from them. */ - if (GET_MODE (x) == XFmode + if ((GET_MODE (x) == XFmode || GET_MODE (x) == TFmode) && x86_ext_80387_constants & TUNEMASK) { REAL_VALUE_TYPE r; @@ -4388,7 +4389,8 @@ standard_80387_constant_rtx (idx) abort (); } - return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i], XFmode); + return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i], + TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode); } /* Return 1 if X is FP constant we can load to SSE register w/o using memory. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index dc4ece8534a..9d0ea2447c7 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -15613,7 +15613,7 @@ UNSPEC_FPATAN)) (clobber (match_dup 1))])] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" + && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE" "fpatan" [(set_attr "type" "fpspc") (set_attr "mode" "XF")]) @@ -15625,7 +15625,7 @@ UNSPEC_FPATAN)) (clobber (match_dup 1))])] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" + && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE" "fpatan" [(set_attr "type" "fpspc") (set_attr "mode" "XF")]) @@ -15633,11 +15633,12 @@ (define_insn "*fyl2x_sfxf3" [(parallel [(set (match_operand:SF 0 "register_operand" "=f") (unspec:SF [(match_operand:SF 2 "register_operand" "0") - (match_operand:XF 1 "register_operand" "u")] + (match_operand 1 "register_operand" "u")] UNSPEC_FYL2X)) (clobber (match_dup 1))])] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" + && flag_unsafe_math_optimizations + && GET_MODE (operands[1]) == TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode" "fyl2x" [(set_attr "type" "fpspc") (set_attr "mode" "SF")]) @@ -15645,11 +15646,12 @@ (define_insn "*fyl2x_dfxf3" [(parallel [(set (match_operand:DF 0 "register_operand" "=f") (unspec:DF [(match_operand:DF 2 "register_operand" "0") - (match_operand:XF 1 "register_operand" "u")] + (match_operand 1 "register_operand" "u")] UNSPEC_FYL2X)) (clobber (match_dup 1))])] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" + && flag_unsafe_math_optimizations + && GET_MODE (operands[1]) == TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode" "fyl2x" [(set_attr "type" "fpspc") (set_attr "mode" "DF")]) @@ -15661,7 +15663,7 @@ UNSPEC_FYL2X)) (clobber (match_dup 1))])] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" + && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE" "fyl2x" [(set_attr "type" "fpspc") (set_attr "mode" "XF")]) @@ -15669,11 +15671,11 @@ (define_insn "*fyl2x_tfxf3" [(parallel [(set (match_operand:TF 0 "register_operand" "=f") (unspec:TF [(match_operand:TF 2 "register_operand" "0") - (match_operand:XF 1 "register_operand" "u")] + (match_operand:TF 1 "register_operand" "u")] UNSPEC_FYL2X)) (clobber (match_dup 1))])] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" + && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE" "fyl2x" [(set_attr "type" "fpspc") (set_attr "mode" "XF")]) @@ -15688,7 +15690,7 @@ { rtx temp; - operands[2] = gen_reg_rtx (XFmode); + operands[2] = gen_reg_rtx (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode); temp = standard_80387_constant_rtx (4); /* fldln2 */ emit_move_insn (operands[2], temp); }) @@ -15703,7 +15705,7 @@ { rtx temp; - operands[2] = gen_reg_rtx (XFmode); + operands[2] = gen_reg_rtx (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode); temp = standard_80387_constant_rtx (4); /* fldln2 */ emit_move_insn (operands[2], temp); }) @@ -15714,7 +15716,7 @@ (match_dup 2)] UNSPEC_FYL2X)) (clobber (match_dup 2))])] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" + && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE" { rtx temp; @@ -15729,35 +15731,39 @@ (match_dup 2)] UNSPEC_FYL2X)) (clobber (match_dup 2))])] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" + && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE" { rtx temp; - operands[2] = gen_reg_rtx (XFmode); + operands[2] = gen_reg_rtx (TFmode); temp = standard_80387_constant_rtx (4); /* fldln2 */ emit_move_insn (operands[2], temp); }) (define_insn "*fscale_sfxf3" [(parallel [(set (match_operand:SF 0 "register_operand" "=f") - (unspec:SF [(match_operand:XF 2 "register_operand" "0") - (match_operand:XF 1 "register_operand" "u")] + (unspec:SF [(match_operand 2 "register_operand" "0") + (match_operand 1 "register_operand" "u")] UNSPEC_FSCALE)) (clobber (match_dup 1))])] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" + && flag_unsafe_math_optimizations + && GET_MODE (operands[1]) == TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode + && GET_MODE (operands[2]) == TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode" "fscale\;fstp\t%y1" [(set_attr "type" "fpspc") (set_attr "mode" "SF")]) (define_insn "*fscale_dfxf3" [(parallel [(set (match_operand:DF 0 "register_operand" "=f") - (unspec:DF [(match_operand:XF 2 "register_operand" "0") - (match_operand:XF 1 "register_operand" "u")] + (unspec:DF [(match_operand 2 "register_operand" "0") + (match_operand 1 "register_operand" "u")] UNSPEC_FSCALE)) (clobber (match_dup 1))])] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" + && flag_unsafe_math_optimizations + && GET_MODE (operands[1]) == TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode + && GET_MODE (operands[2]) == TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode" "fscale\;fstp\t%y1" [(set_attr "type" "fpspc") (set_attr "mode" "DF")]) @@ -15769,7 +15775,19 @@ UNSPEC_FSCALE)) (clobber (match_dup 1))])] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" + && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE" + "fscale\;fstp\t%y1" + [(set_attr "type" "fpspc") + (set_attr "mode" "XF")]) + +(define_insn "*fscale_tf3" + [(parallel [(set (match_operand:TF 0 "register_operand" "=f") + (unspec:TF [(match_operand:TF 2 "register_operand" "0") + (match_operand:TF 1 "register_operand" "u")] + UNSPEC_FSCALE)) + (clobber (match_dup 1))])] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE" "fscale\;fstp\t%y1" [(set_attr "type" "fpspc") (set_attr "mode" "XF")]) @@ -15779,7 +15797,17 @@ (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_FRNDINT))] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" + && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE" + "frndint" + [(set_attr "type" "fpspc") + (set_attr "mode" "XF")]) + +(define_insn "*frndinttf2" + [(set (match_operand:TF 0 "register_operand" "=f") + (unspec:TF [(match_operand:TF 1 "register_operand" "0")] + UNSPEC_FRNDINT))] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE" "frndint" [(set_attr "type" "fpspc") (set_attr "mode" "XF")]) @@ -15789,7 +15817,17 @@ (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_F2XM1))] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" + && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE" + "f2xm1" + [(set_attr "type" "fpspc") + (set_attr "mode" "XF")]) + +(define_insn "*f2xm1tf2" + [(set (match_operand:TF 0 "register_operand" "=f") + (unspec:TF [(match_operand:TF 1 "register_operand" "0")] + UNSPEC_F2XM1))] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE" "f2xm1" [(set_attr "type" "fpspc") (set_attr "mode" "XF")]) @@ -15811,6 +15849,12 @@ rtx temp; int i; + if (TARGET_128BIT_LONG_DOUBLE) + { + emit_insn (gen_expsf2_tf (operands[0], operands[1])); + DONE; + } + for (i=2; i<10; i++) operands[i] = gen_reg_rtx (XFmode); temp = standard_80387_constant_rtx (5); /* fldl2e */ @@ -15818,6 +15862,29 @@ emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */ }) +(define_expand "expsf2_tf" + [(set (match_dup 2) + (float_extend:TF (match_operand:SF 1 "register_operand" ""))) + (set (match_dup 4) (mult:TF (match_dup 2) (match_dup 3))) + (set (match_dup 5) (unspec:TF [(match_dup 4)] UNSPEC_FRNDINT)) + (set (match_dup 6) (minus:TF (match_dup 4) (match_dup 5))) + (set (match_dup 7) (unspec:TF [(match_dup 6)] UNSPEC_F2XM1)) + (set (match_dup 9) (plus:TF (match_dup 7) (match_dup 8))) + (parallel [(set (match_operand:SF 0 "register_operand" "") + (unspec:SF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE)) + (clobber (match_dup 5))])] + "" +{ + rtx temp; + int i; + + for (i=2; i<10; i++) + operands[i] = gen_reg_rtx (TFmode); + temp = standard_80387_constant_rtx (5); /* fldl2e */ + emit_move_insn (operands[3], temp); + emit_move_insn (operands[8], CONST1_RTX (TFmode)); /* fld1 */ +}) + (define_expand "expdf2" [(set (match_dup 2) (float_extend:XF (match_operand:DF 1 "register_operand" ""))) @@ -15835,6 +15902,12 @@ rtx temp; int i; + if (TARGET_128BIT_LONG_DOUBLE) + { + emit_insn (gen_expdf2_tf (operands[0], operands[1])); + DONE; + } + for (i=2; i<10; i++) operands[i] = gen_reg_rtx (XFmode); temp = standard_80387_constant_rtx (5); /* fldl2e */ @@ -15842,6 +15915,30 @@ emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */ }) + +(define_expand "expdf2_tf" + [(set (match_dup 2) + (float_extend:TF (match_operand:DF 1 "register_operand" ""))) + (set (match_dup 4) (mult:TF (match_dup 2) (match_dup 3))) + (set (match_dup 5) (unspec:TF [(match_dup 4)] UNSPEC_FRNDINT)) + (set (match_dup 6) (minus:TF (match_dup 4) (match_dup 5))) + (set (match_dup 7) (unspec:TF [(match_dup 6)] UNSPEC_F2XM1)) + (set (match_dup 9) (plus:TF (match_dup 7) (match_dup 8))) + (parallel [(set (match_operand:DF 0 "register_operand" "") + (unspec:DF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE)) + (clobber (match_dup 5))])] + "" +{ + rtx temp; + int i; + + for (i=2; i<10; i++) + operands[i] = gen_reg_rtx (TFmode); + temp = standard_80387_constant_rtx (5); /* fldl2e */ + emit_move_insn (operands[3], temp); + emit_move_insn (operands[8], CONST1_RTX (TFmode)); /* fld1 */ +}) + (define_expand "expxf2" [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "") (match_dup 2))) @@ -15853,7 +15950,7 @@ (unspec:XF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE)) (clobber (match_dup 4))])] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" + && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE" { rtx temp; int i; @@ -15878,6 +15975,29 @@ emit_move_insn (operands[2], CONST1_RTX (SFmode)); /* fld1 */ }) +(define_expand "exptf2" + [(set (match_dup 3) (mult:TF (match_operand:TF 1 "register_operand" "") + (match_dup 2))) + (set (match_dup 4) (unspec:TF [(match_dup 3)] UNSPEC_FRNDINT)) + (set (match_dup 5) (minus:TF (match_dup 3) (match_dup 4))) + (set (match_dup 6) (unspec:TF [(match_dup 5)] UNSPEC_F2XM1)) + (set (match_dup 8) (plus:TF (match_dup 6) (match_dup 7))) + (parallel [(set (match_operand:TF 0 "register_operand" "") + (unspec:TF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE)) + (clobber (match_dup 4))])] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE" +{ + rtx temp; + int i; + + for (i=2; i<9; i++) + operands[i] = gen_reg_rtx (TFmode); + temp = standard_80387_constant_rtx (5); /* fldl2e */ + emit_move_insn (operands[2], temp); + emit_move_insn (operands[7], CONST1_RTX (TFmode)); /* fld1 */ +}) + (define_expand "atandf2" [(parallel [(set (match_operand:DF 0 "register_operand" "") (unspec:DF [(match_dup 2) @@ -15898,7 +16018,7 @@ UNSPEC_FPATAN)) (clobber (match_dup 1))])] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" + && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE" { operands[2] = gen_reg_rtx (XFmode); emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */ @@ -15911,7 +16031,7 @@ UNSPEC_FPATAN)) (clobber (match_dup 1))])] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && flag_unsafe_math_optimizations" + && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE" { operands[2] = gen_reg_rtx (TFmode); emit_move_insn (operands[2], CONST1_RTX (TFmode)); /* fld1 */ -- 2.30.2