From 1f52332b8d4621d6c5ab1447e82b6e2e53600e52 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Thu, 16 May 2019 12:53:43 +0200 Subject: [PATCH] Added tests for Verilog frontent for attributes on parameters and localparams Signed-off-by: Maciej Kurc --- tests/simple/localparam_attr.v | 11 +++++++++++ tests/simple/param_attr.v | 11 +++++++++++ 2 files changed, 22 insertions(+) create mode 100644 tests/simple/localparam_attr.v create mode 100644 tests/simple/param_attr.v diff --git a/tests/simple/localparam_attr.v b/tests/simple/localparam_attr.v new file mode 100644 index 000000000..2ef76c71c --- /dev/null +++ b/tests/simple/localparam_attr.v @@ -0,0 +1,11 @@ +module uut_localparam_attr (I, O); + +(* LOCALPARAM_ATTRIBUTE = "attribute_content" *) +localparam WIDTH = 1; + +input wire [WIDTH-1:0] I; +output wire [WIDTH-1:0] O; + +assign O = I; + +endmodule diff --git a/tests/simple/param_attr.v b/tests/simple/param_attr.v new file mode 100644 index 000000000..34d63a34e --- /dev/null +++ b/tests/simple/param_attr.v @@ -0,0 +1,11 @@ +module uut_param_attr (I, O); + +(* PARAMETER_ATTRIBUTE = "attribute_content" *) +parameter WIDTH = 1; + +input wire [WIDTH-1:0] I; +output wire [WIDTH-1:0] O; + +assign O = I; + +endmodule -- 2.30.2