From 1f54946e9b8215d0a26228722ba42f4793325901 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 4 Mar 2019 05:38:45 +0000 Subject: [PATCH] enable single-cycle in FP16 test --- src/add/test_add16.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/add/test_add16.py b/src/add/test_add16.py index 41b35f68..f39ae8ae 100644 --- a/src/add/test_add16.py +++ b/src/add/test_add16.py @@ -39,6 +39,6 @@ def testbench(dut): yield from run_edge_cases(dut, count, add) if __name__ == '__main__': - dut = FPADD(width=16, single_cycle=False) + dut = FPADD(width=16, single_cycle=True) run_simulation(dut, testbench(dut), vcd_name="test_add16.vcd") -- 2.30.2