From 1f58b6ffefaa01f4b36241c2571d9e52b3775bf1 Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Sat, 13 Jul 2019 16:05:40 +0200 Subject: [PATCH] radv/gfx10: Fix DCC clears. Looks like if the reg clear bit is set, the hwardware does not use the 0/1 clears for textures. Reviewed-by: Dave Airlie --- src/amd/vulkan/radv_meta_clear.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 08d9ea3e1db..dd2ba402f40 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1421,6 +1421,12 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value); } +enum { + RADV_DCC_CLEAR_REG = 0x20202020U, + RADV_DCC_CLEAR_MAIN_1 = 0x80808080U, + RADV_DCC_CLEAR_SECONDARY_1 = 0x40404040U +}; + static void vi_get_fast_clear_parameters(VkFormat format, const VkClearColorValue *clear_value, uint32_t* reset_value, @@ -1433,7 +1439,7 @@ static void vi_get_fast_clear_parameters(VkFormat format, int i; *can_avoid_fast_clear_elim = false; - *reset_value = 0x20202020U; + *reset_value = RADV_DCC_CLEAR_REG; const struct vk_format_description *desc = vk_format_description(format); if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 || @@ -1490,11 +1496,12 @@ static void vi_get_fast_clear_parameters(VkFormat format, return; *can_avoid_fast_clear_elim = true; + *reset_value = 0; if (main_value) - *reset_value |= 0x80808080U; + *reset_value |= RADV_DCC_CLEAR_MAIN_1; if (extra_value) - *reset_value |= 0x40404040U; + *reset_value |= RADV_DCC_CLEAR_SECONDARY_1; return; } -- 2.30.2