From 1f6983da2ce9ef45c7788f0829b110f6695b67bf Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 11 Nov 2015 14:22:27 +0100 Subject: [PATCH] soc/cores/liteeth_mini: add phy model for verilator simulation --- litex/soc/cores/liteeth_mini/common.py | 4 +- litex/soc/cores/liteeth_mini/phy/__init__.py | 8 +-- litex/soc/cores/liteeth_mini/phy/gmii.py | 2 +- litex/soc/cores/liteeth_mini/phy/gmii_mii.py | 10 ++-- litex/soc/cores/liteeth_mini/phy/loopback.py | 8 +-- litex/soc/cores/liteeth_mini/phy/mii.py | 6 +- litex/soc/cores/liteeth_mini/phy/model.py | 58 ++++++++++++++++++++ litex/soc/cores/liteeth_mini/phy/s6rgmii.py | 6 +- 8 files changed, 80 insertions(+), 22 deletions(-) create mode 100644 litex/soc/cores/liteeth_mini/phy/model.py diff --git a/litex/soc/cores/liteeth_mini/common.py b/litex/soc/cores/liteeth_mini/common.py index 4638c76c..3f16e91c 100644 --- a/litex/soc/cores/liteeth_mini/common.py +++ b/litex/soc/cores/liteeth_mini/common.py @@ -1,8 +1,8 @@ from migen import * from migen.genlib.record import * -from misoc.interconnect.csr import * -from misoc.interconnect.stream import * +from litex.soc.interconnect.csr import * +from litex.soc.interconnect.stream import * class Port: diff --git a/litex/soc/cores/liteeth_mini/phy/__init__.py b/litex/soc/cores/liteeth_mini/phy/__init__.py index a5d5ae92..8174a566 100644 --- a/litex/soc/cores/liteeth_mini/phy/__init__.py +++ b/litex/soc/cores/liteeth_mini/phy/__init__.py @@ -1,4 +1,4 @@ -from misoc.cores.liteeth_mini.common import * +from litex.soc.cores.liteeth_mini.common import * def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs): @@ -6,18 +6,18 @@ def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs): if hasattr(clock_pads, "gtx") and len(pads.tx_data) == 8: if hasattr(clock_pads, "tx"): # This is a 10/100/1G PHY - from misoc.cores.liteeth_mini.phy.gmii_mii import LiteEthPHYGMIIMII + from litex.soc.cores.liteeth_mini.phy.gmii_mii import LiteEthPHYGMIIMII return LiteEthPHYGMIIMII(clock_pads, pads, clk_freq=clk_freq, **kwargs) else: # This is a pure 1G PHY - from misoc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMII + from litex.soc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMII return LiteEthPHYGMII(clock_pads, pads, **kwargs) elif hasattr(pads, "rx_ctl"): # This is a 10/100/1G RGMII PHY raise ValueError("RGMII PHYs are specific to vendors (for now), use direct instantiation") elif len(pads.tx_data) == 4: # This is a MII PHY - from misoc.cores.liteeth_mini.phy.mii import LiteEthPHYMII + from litex.soc.cores.liteeth_mini.phy.mii import LiteEthPHYMII return LiteEthPHYMII(clock_pads, pads, **kwargs) else: raise ValueError("Unable to autodetect PHY from platform file, use direct instantiation") diff --git a/litex/soc/cores/liteeth_mini/phy/gmii.py b/litex/soc/cores/liteeth_mini/phy/gmii.py index bb3fc0bb..e73cc341 100644 --- a/litex/soc/cores/liteeth_mini/phy/gmii.py +++ b/litex/soc/cores/liteeth_mini/phy/gmii.py @@ -2,7 +2,7 @@ from migen import * from migen.genlib.io import DDROutput from migen.genlib.resetsync import AsyncResetSynchronizer -from misoc.cores.liteeth_mini.common import * +from litex.soc.cores.liteeth_mini.common import * class LiteEthPHYGMIITX(Module): diff --git a/litex/soc/cores/liteeth_mini/phy/gmii_mii.py b/litex/soc/cores/liteeth_mini/phy/gmii_mii.py index 6946c6c3..4ea06eec 100644 --- a/litex/soc/cores/liteeth_mini/phy/gmii_mii.py +++ b/litex/soc/cores/liteeth_mini/phy/gmii_mii.py @@ -2,11 +2,11 @@ from migen import * from migen.genlib.io import DDROutput from migen.genlib.cdc import PulseSynchronizer -from misoc.interconnect.stream import * -from misoc.cores.liteeth_mini.common import * -from misoc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMIICRG -from misoc.cores.liteeth_mini.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX -from misoc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX +from litex.soc.interconnect.stream import * +from litex.soc.cores.liteeth_mini.common import * +from litex.soc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMIICRG +from litex.soc.cores.liteeth_mini.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX +from litex.soc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX modes = { diff --git a/litex/soc/cores/liteeth_mini/phy/loopback.py b/litex/soc/cores/liteeth_mini/phy/loopback.py index 28b1430e..fd7583c6 100644 --- a/litex/soc/cores/liteeth_mini/phy/loopback.py +++ b/litex/soc/cores/liteeth_mini/phy/loopback.py @@ -1,9 +1,9 @@ from migen import * -from misoc.interconnect.csr import * -from misoc.interconnect.stream import * -from misoc.cores.liteeth_mini.common import * -from misoc.cores.liteeth.mini.generic import * +from litex.soc.interconnect.csr import * +from litex.soc.interconnect.stream import * +from litex.soc.cores.liteeth_mini.common import * +from litex.soc.cores.liteeth.mini.generic import * class LiteEthPHYLoopbackCRG(Module, AutoCSR): diff --git a/litex/soc/cores/liteeth_mini/phy/mii.py b/litex/soc/cores/liteeth_mini/phy/mii.py index c5bf5271..5072091a 100644 --- a/litex/soc/cores/liteeth_mini/phy/mii.py +++ b/litex/soc/cores/liteeth_mini/phy/mii.py @@ -1,8 +1,8 @@ from migen import * -from misoc.interconnect.csr import * -from misoc.interconnect.stream import * -from misoc.cores.liteeth_mini.common import * +from litex.soc.interconnect.csr import * +from litex.soc.interconnect.stream import * +from litex.soc.cores.liteeth_mini.common import * def converter_description(dw): diff --git a/litex/soc/cores/liteeth_mini/phy/model.py b/litex/soc/cores/liteeth_mini/phy/model.py new file mode 100644 index 00000000..6deed17e --- /dev/null +++ b/litex/soc/cores/liteeth_mini/phy/model.py @@ -0,0 +1,58 @@ +import os + +from litex.soc.cores.liteeth_mini.common import * + + +class LiteEthPHYModelCRG(Module, AutoCSR): + def __init__(self): + self._reset = CSRStorage() + + # # # + + self.clock_domains.cd_eth_rx = ClockDomain() + self.clock_domains.cd_eth_tx = ClockDomain() + self.comb += [ + self.cd_eth_rx.clk.eq(ClockSignal()), + self.cd_eth_tx.clk.eq(ClockSignal()) + ] + + reset = self._reset.storage + self.comb += [ + self.cd_eth_rx.rst.eq(reset), + self.cd_eth_tx.rst.eq(reset) + ] + + +class LiteEthPHYModel(Module, AutoCSR): + def __init__(self, pads, tap="tap0", ip_address="192.168.0.14"): + self.dw = 8 + self.submodules.crg = LiteEthPHYModelCRG() + self.sink = sink = Sink(eth_phy_description(8)) + self.source = source = Source(eth_phy_description(8)) + self.tap = tap + self.ip_address = ip_address + + self.comb += [ + pads.source_stb.eq(self.sink.stb), + pads.source_data.eq(self.sink.data), + self.sink.ack.eq(1) + ] + + self.sync += [ + self.source.stb.eq(pads.sink_stb), + self.source.sop.eq(pads.sink_stb & ~self.source.stb), + self.source.data.eq(pads.sink_data), + ] + self.comb += [ + self.source.eop.eq(~pads.sink_stb & self.source.stb), + ] + + # TODO avoid use of os.system + os.system("openvpn --mktun --dev {}".format(self.tap)) + os.system("ifconfig {} {} up".format(self.tap, self.ip_address)) + os.system("mknod /dev/net/{} c 10 200".format(self.tap)) + + def do_exit(self, *args, **kwargs): + # TODO avoid use of os.system + os.system("rm -f /dev/net/{}".format(self.tap)) + os.system("openvpn --rmtun --dev {}".format(self.tap)) diff --git a/litex/soc/cores/liteeth_mini/phy/s6rgmii.py b/litex/soc/cores/liteeth_mini/phy/s6rgmii.py index 1f312ace..b2b2876a 100644 --- a/litex/soc/cores/liteeth_mini/phy/s6rgmii.py +++ b/litex/soc/cores/liteeth_mini/phy/s6rgmii.py @@ -5,9 +5,9 @@ from migen.genlib.io import DDROutput from migen.genlib.misc import WaitTimer from migen.genlib.fsm import FSM, NextState -from misoc.interconnect.stream import * -from misoc.interconnect.csr import * -from misoc.cores.liteeth_mini.common import * +from litex.soc.interconnect.stream import * +from litex.soc.interconnect.csr import * +from litex.soc.cores.liteeth_mini.common import * class LiteEthPHYRGMIITX(Module): -- 2.30.2