From 1f84e73575dc2f64f2e434a7b9fc6b91bfd73f71 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 11 Jun 2020 11:31:05 +0100 Subject: [PATCH] read and write version of get_sim_xer_ca are different --- src/soc/fu/alu/test/test_pipe_caller.py | 4 ++-- src/soc/fu/test/common.py | 9 ++++++++- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index 62a1d0b6..83377e9f 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -25,7 +25,7 @@ def get_cu_inputs(dec2, sim): yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB - yield from ALUHelpers.get_sim_xer_ca(res, sim, dec2) # XER.ca + yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so print ("alu get_cu_inputs", res) @@ -276,7 +276,7 @@ class TestRunner(FHDLTestCase): yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2) - yield from ALUHelpers.get_sim_xer_ca(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2) yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2) ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code)) diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py index 9569dfd9..b6ba048f 100644 --- a/src/soc/fu/test/common.py +++ b/src/soc/fu/test/common.py @@ -69,6 +69,13 @@ class ALUHelpers: data = yield dec2.e.read_reg3.data res['rc'] = sim.gpr(data).value + def get_rd_sim_xer_ca(res, sim, dec2): + cry_in = yield dec2.e.input_carry + if cry_in: + expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0 + expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0 + res['xer_ca'] = expected_carry | (expected_carry32 << 1) + def set_int_ra(alu, dec2, inp): # TODO: immediate RA zero. if 'ra' in inp: @@ -172,7 +179,7 @@ class ALUHelpers: cridx = yield dec2.e.write_cr.data res['cr_a'] = sim.crl[cridx].get_range().value - def get_sim_xer_ca(res, sim, dec2): + def get_wr_sim_xer_ca(res, sim, dec2): cry_out = yield dec2.e.output_carry if cry_out: expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0 -- 2.30.2