From 1fa0b332ca241f4ae253fe29326147cf3ebcdade Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Tue, 27 Aug 2019 12:02:00 +1000 Subject: [PATCH] micropython only requires 512kB of BRAM Mikey points out that our stack grows down from 512kB and our heap is below that too, so we can reduce our BRAM requirements, which allowing some smaller FPGA boards to work. Not sure why I thought we were using memory between 512kB and 1MB. Signed-off-by: Anton Blanchard --- core_tb.vhdl | 2 +- fpga/toplevel.vhd | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/core_tb.vhdl b/core_tb.vhdl index 1c463d7..68359a3 100644 --- a/core_tb.vhdl +++ b/core_tb.vhdl @@ -26,7 +26,7 @@ begin wishbone_out => wishbone_out, registers => registers, terminate_out => terminate); simple_ram_0: entity work.simple_ram_behavioural - generic map ( filename => "simple_ram_behavioural.bin", size => 1048576) + generic map ( filename => "simple_ram_behavioural.bin", size => 524288) port map (clk => clk, rst => rst, wishbone_in => wishbone_out, wishbone_out => wishbone_in); clk_process: process diff --git a/fpga/toplevel.vhd b/fpga/toplevel.vhd index 17842c8..ba41b31 100644 --- a/fpga/toplevel.vhd +++ b/fpga/toplevel.vhd @@ -13,7 +13,7 @@ use work.wishbone_types.all; -- 0xc0002000: UART0 (for host communication) entity toplevel is generic ( - MEMORY_SIZE : positive := 1048576; + MEMORY_SIZE : positive := 524288; RAM_INIT_FILE : string := "firmware.hex"); port( clk : in std_logic; -- 2.30.2