From 1fae20c5f3991187c13a80326c5f27ab8afc5f83 Mon Sep 17 00:00:00 2001 From: Staf Verhaegen Date: Wed, 4 Dec 2019 17:36:22 +0100 Subject: [PATCH] Fix code after move * tests fixed * path to vhdl source --- c4m/nmigen/jtag/jtag.py | 4 ++-- test/cocotb/controller/Makefile | 18 +++++++++++++----- test/cocotb/controller/c4m_jtag.py | 1 - test/cocotb/controller/test.py | 2 +- test/cocotb/dual_parallel/Makefile | 20 ++++++++++++++------ test/cocotb/dual_parallel/c4m_jtag.py | 1 - test/cocotb/dual_parallel/test.py | 2 +- test/ghdl/idcode/bench_idcode.sh | 21 ++++++++++++--------- 8 files changed, 43 insertions(+), 26 deletions(-) delete mode 120000 test/cocotb/controller/c4m_jtag.py delete mode 120000 test/cocotb/dual_parallel/c4m_jtag.py diff --git a/c4m/nmigen/jtag/jtag.py b/c4m/nmigen/jtag/jtag.py index 3baaa95..88d1292 100755 --- a/c4m/nmigen/jtag/jtag.py +++ b/c4m/nmigen/jtag/jtag.py @@ -216,8 +216,8 @@ class JTAGWishbone(Elaboratable): class JTAG(Elaboratable): @staticmethod def _add_files(platform, prefix): - d = os.path.realpath("{0}{1}{2}{1}vhdl".format( - os.path.dirname(__file__), os.path.sep, os.path.pardir + d = os.path.realpath("{dir}{sep}{par}{sep}{par}{sep}vhdl{sep}jtag".format( + dir=os.path.dirname(__file__), sep=os.path.sep, par=os.path.pardir )) + os.path.sep for fname in [ "c4m_jtag_pkg.vhdl", diff --git a/test/cocotb/controller/Makefile b/test/cocotb/controller/Makefile index 708e50d..08b5659 100644 --- a/test/cocotb/controller/Makefile +++ b/test/cocotb/controller/Makefile @@ -1,6 +1,14 @@ -PWD=$(realpath .) +CURDIR=$(realpath .) TOPDIR=$(realpath ../../..) -VHDLDIR=$(TOPDIR)/rtl/vhdl + +ifeq ($(PYTHONPATH),) + PYTHONPATH := $(TOPDIR) +else + PYTHONPATH := $(TOPDIR):$(PYTHONPATH) +endif +export PYTHONPATH + +VHDLDIR=$(TOPDIR)/c4m/vhdl/jtag VHDL_SOURCES = \ $(VHDLDIR)/c4m_jtag_pkg.vhdl \ $(VHDLDIR)/c4m_jtag_tap_fsm.vhdl \ @@ -16,7 +24,7 @@ SIM=ghdl GPI_IMPL=vhpi SIM_ARGS=--wave=test.ghw -COCOTBDIR=$(shell cocotb-path) +COCOTBMAKEFILESDIR=$(shell cocotb-config --makefiles) -include $(COCOTBDIR)/makefiles/Makefile.inc -include $(COCOTBDIR)/makefiles/Makefile.sim +include $(COCOTBMAKEFILESDIR)/Makefile.inc +include $(COCOTBMAKEFILESDIR)/Makefile.sim diff --git a/test/cocotb/controller/c4m_jtag.py b/test/cocotb/controller/c4m_jtag.py deleted file mode 120000 index f409baa..0000000 --- a/test/cocotb/controller/c4m_jtag.py +++ /dev/null @@ -1 +0,0 @@ -../c4m_jtag.py \ No newline at end of file diff --git a/test/cocotb/controller/test.py b/test/cocotb/controller/test.py index 9d66ea8..4772194 100644 --- a/test/cocotb/controller/test.py +++ b/test/cocotb/controller/test.py @@ -2,7 +2,7 @@ import cocotb from cocotb.utils import get_sim_steps from cocotb.binary import BinaryValue -from c4m_jtag import JTAG_Master +from c4m.cocotb.jtag.c4m_jtag import JTAG_Master @cocotb.test() def test01_idcode(dut): diff --git a/test/cocotb/dual_parallel/Makefile b/test/cocotb/dual_parallel/Makefile index e7da7cd..383a1ba 100644 --- a/test/cocotb/dual_parallel/Makefile +++ b/test/cocotb/dual_parallel/Makefile @@ -1,6 +1,14 @@ -PWD=$(realpath .) +CURDIR=$(realpath .) TOPDIR=$(realpath ../../..) -VHDLDIR=$(TOPDIR)/rtl/vhdl + +ifeq ($(PYTHONPATH),) + PYTHONPATH := $(TOPDIR) +else + PYTHONPATH := $(TOPDIR):$(PYTHONPATH) +endif +export PYTHONPATH + +VHDLDIR=$(TOPDIR)/c4m/vhdl/jtag VHDL_SOURCES = \ $(VHDLDIR)/c4m_jtag_pkg.vhdl \ $(VHDLDIR)/c4m_jtag_tap_fsm.vhdl \ @@ -9,7 +17,7 @@ VHDL_SOURCES = \ $(VHDLDIR)/c4m_jtag_ioblock.vhdl \ $(VHDLDIR)/c4m_jtag_idblock.vhdl \ $(VHDLDIR)/c4m_jtag_tap_controller.vhdl \ - $(PWD)/dual_parallel.vhdl + $(CURDIR)/dual_parallel.vhdl TOPLEVEL=dual_parallel TOPLEVEL_LANG=vhdl MODULE=test @@ -17,7 +25,7 @@ SIM=ghdl GPI_IMPL=vhpi SIM_ARGS=--wave=test.ghw -COCOTBDIR=$(shell cocotb-path) +COCOTBMAKEFILESDIR=$(shell cocotb-config --makefiles) -include $(COCOTBDIR)/makefiles/Makefile.inc -include $(COCOTBDIR)/makefiles/Makefile.sim +include $(COCOTBMAKEFILESDIR)/Makefile.inc +include $(COCOTBMAKEFILESDIR)/Makefile.sim diff --git a/test/cocotb/dual_parallel/c4m_jtag.py b/test/cocotb/dual_parallel/c4m_jtag.py deleted file mode 120000 index f409baa..0000000 --- a/test/cocotb/dual_parallel/c4m_jtag.py +++ /dev/null @@ -1 +0,0 @@ -../c4m_jtag.py \ No newline at end of file diff --git a/test/cocotb/dual_parallel/test.py b/test/cocotb/dual_parallel/test.py index 47cf306..77e225d 100644 --- a/test/cocotb/dual_parallel/test.py +++ b/test/cocotb/dual_parallel/test.py @@ -1,7 +1,7 @@ import cocotb from cocotb.utils import get_sim_steps -from c4m_jtag import JTAG_Master +from c4m.cocotb.jtag.c4m_jtag import JTAG_Master @cocotb.test() def test01_dual(dut): diff --git a/test/ghdl/idcode/bench_idcode.sh b/test/ghdl/idcode/bench_idcode.sh index e17b656..6462c41 100755 --- a/test/ghdl/idcode/bench_idcode.sh +++ b/test/ghdl/idcode/bench_idcode.sh @@ -1,10 +1,13 @@ #!/bin/sh -ghdl -a --std=08 ../../rtl/vhdl/c4m_jtag_pkg.vhdl -ghdl -a --std=08 ../../rtl/vhdl/c4m_jtag_tap_fsm.vhdl -ghdl -a --std=08 ../../rtl/vhdl/c4m_jtag_irblock.vhdl -ghdl -a --std=08 ../../rtl/vhdl/c4m_jtag_idblock.vhdl -ghdl -a --std=08 ../../rtl/vhdl/c4m_jtag_iocell.vhdl -ghdl -a --std=08 ../../rtl/vhdl/c4m_jtag_ioblock.vhdl -ghdl -a --std=08 ../../rtl/vhdl/c4m_jtag_tap_controller.vhdl -ghdl -a --std=08 ../../bench/vhdl/idcode.vhdl -ghdl -r --std=08 bench_idcode --wave=bench_idcode.ghw +vhdldir=`realpath ../../../c4m/vhdl/jtag` +testvhdldir=`realpath ../../rtl/vhdl` +opts=--std=08 +ghdl -a $opts $vhdldir/c4m_jtag_pkg.vhdl +ghdl -a $opts $vhdldir/c4m_jtag_tap_fsm.vhdl +ghdl -a $opts $vhdldir/c4m_jtag_irblock.vhdl +ghdl -a $opts $vhdldir/c4m_jtag_idblock.vhdl +ghdl -a $opts $vhdldir/c4m_jtag_iocell.vhdl +ghdl -a $opts $vhdldir/c4m_jtag_ioblock.vhdl +ghdl -a $opts $vhdldir/c4m_jtag_tap_controller.vhdl +ghdl -a $opts $testvhdldir/idcode.vhdl +ghdl -r $opts bench_idcode --wave=bench_idcode.ghw -- 2.30.2