From 1fb4bbf9b76bc0bcc6a58f075782c43cb4393218 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 18 Apr 2023 22:57:41 +0100 Subject: [PATCH] Revert "fix extsb pseudo-code" This reverts commit 3683d40d020ca785168fb059f75e7159cc904ab1. --- openpower/sv/rfc/ls005.mdwn | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/openpower/sv/rfc/ls005.mdwn b/openpower/sv/rfc/ls005.mdwn index b8ea786c2..6611f89f8 100644 --- a/openpower/sv/rfc/ls005.mdwn +++ b/openpower/sv/rfc/ls005.mdwn @@ -284,19 +284,14 @@ is a loss of functionality and opportunity: extsw: 32-bit -> 64-bit sign extension ``` -The pseudo-code for `extsb` becomes: +The RTL for `extsb` becomes: ``` -RT[0:XLEN-1] <- EXTS((RA)[XLEN*7/8:XLEN-1]) -``` - -or, if expanded out: - -``` - if XLEN = 8 then RT <- (RA)[ 7] * 7 || (RA)[ 7: 7] # 1 -> 8 - if XLEN = 16 then RT <- (RA)[14] * 14 || (RA)[14:15] # 2 -> 16 - if XLEN = 32 then RT <- (RA)[28] * 28 || (RA)[28:31] # 4 -> 32 - if XLEN = 64 then RT <- (RA)[56] * 56 || (RA)[56:63] # 8 -> 64 + in <- (RA)[XLEN-8:XLEN-1] + if XLEN = 8 then RT <- in[0]] * 8 # 1->8 + if XLEN = 16 then RT <- in[13]] * 15 || in[15] # 2->16 + if XLEN = 32 then RT <- in[28]] * 29 || in[29:31] # 4->32 + if XLEN = 64 then RT <- in[55]] * 56 || in[57:63] # 8->64 ``` And `extsh` and `extsw` follow similar logic. Interestingly there is -- 2.30.2