From 1fc061d90c45166f87d92f76b6fae1ec517be72f Mon Sep 17 00:00:00 2001
From: dh73 <dh73_fpga@qq.com>
Date: Wed, 8 Nov 2017 20:23:55 -0600
Subject: [PATCH] Organizing Speedster file names

---
 techlibs/achronix/Makefile.inc                                | 4 ++--
 .../speedster22i/{cells_arith_speedster.v => cells_arith.v}   | 0
 .../speedster22i/{cells_map_speedster.v => cells_map.v}       | 0
 .../speedster22i/{cells_comb_speedster.v => cells_sim.v}      | 0
 techlibs/achronix/synth_speedster.cc                          | 4 ++--
 5 files changed, 4 insertions(+), 4 deletions(-)
 rename techlibs/achronix/speedster22i/{cells_arith_speedster.v => cells_arith.v} (100%)
 rename techlibs/achronix/speedster22i/{cells_map_speedster.v => cells_map.v} (100%)
 rename techlibs/achronix/speedster22i/{cells_comb_speedster.v => cells_sim.v} (100%)

diff --git a/techlibs/achronix/Makefile.inc b/techlibs/achronix/Makefile.inc
index 4dfa59856..affe0334a 100755
--- a/techlibs/achronix/Makefile.inc
+++ b/techlibs/achronix/Makefile.inc
@@ -1,6 +1,6 @@
 
 OBJS += techlibs/achronix/synth_speedster.o
 
-$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_comb_speedster.v))
-$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map_speedster.v))
+$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_sim.v))
+$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map.v))
 
diff --git a/techlibs/achronix/speedster22i/cells_arith_speedster.v b/techlibs/achronix/speedster22i/cells_arith.v
similarity index 100%
rename from techlibs/achronix/speedster22i/cells_arith_speedster.v
rename to techlibs/achronix/speedster22i/cells_arith.v
diff --git a/techlibs/achronix/speedster22i/cells_map_speedster.v b/techlibs/achronix/speedster22i/cells_map.v
similarity index 100%
rename from techlibs/achronix/speedster22i/cells_map_speedster.v
rename to techlibs/achronix/speedster22i/cells_map.v
diff --git a/techlibs/achronix/speedster22i/cells_comb_speedster.v b/techlibs/achronix/speedster22i/cells_sim.v
similarity index 100%
rename from techlibs/achronix/speedster22i/cells_comb_speedster.v
rename to techlibs/achronix/speedster22i/cells_sim.v
diff --git a/techlibs/achronix/synth_speedster.cc b/techlibs/achronix/synth_speedster.cc
index 8158c56fd..3808af6f1 100755
--- a/techlibs/achronix/synth_speedster.cc
+++ b/techlibs/achronix/synth_speedster.cc
@@ -122,7 +122,7 @@ struct SynthIntelPass : public ScriptPass {
   {
     if (check_label("begin"))
       {
-        run("read_verilog -sv -lib +/achronix/speedster22i/cells_comb_speedster.v");
+        run("read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v");
         run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
       }
 
@@ -164,7 +164,7 @@ struct SynthIntelPass : public ScriptPass {
     if (check_label("map_cells"))
       {
         run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I");
-        run("techmap -map +/achronix/speedster22i/cells_map_speedster.v");
+        run("techmap -map +/achronix/speedster22i/cells_map.v");
         run("dffinit -ff dffeas Q INIT");
         run("clean -purge");
       }
-- 
2.30.2