From 1feba2cdf64e2958e3f3e160c68d5ac049b8d344 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 21 Jan 2022 13:06:31 +0000
Subject: [PATCH] going to be adding verilator save/restore state however the
 simulated-uart will be in some unknown state at the time, on restore.  as a
 "cheat", only save when the tx and rx state machines are both in IDLE

---
 verilator/uart-verilator.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/verilator/uart-verilator.c b/verilator/uart-verilator.c
index 8492a11..0346f6b 100644
--- a/verilator/uart-verilator.c
+++ b/verilator/uart-verilator.c
@@ -251,3 +251,11 @@ unsigned char uart_rx(void)
 
 	return rx;
 }
+
+// cheating, here: to avoid having to save the uart state, check if it
+// is idle (both tx and rx)
+bool uart_idle(void)
+{
+	return (tx_state == IDLE && rx_state == IDLE);
+}
+
-- 
2.30.2