From 1ff2a70ec87c0a418ca38cdff9b14fc29e4b1ecb Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 31 Jul 2018 11:26:47 -0700 Subject: [PATCH] Make sstatus.MXR readable h/t @taoliug --- riscv/processor.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index 52f69c1..2a4a18c 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -584,7 +584,7 @@ reg_t processor_t::get_csr(int which) case CSR_MCOUNTEREN: return state.mcounteren; case CSR_SSTATUS: { reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS - | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL; + | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_UXL; reg_t sstatus = state.mstatus & mask; if ((sstatus & SSTATUS_FS) == SSTATUS_FS || (sstatus & SSTATUS_XS) == SSTATUS_XS) -- 2.30.2