From 1ff8e4010580a425e5f4e7bd14471154b2ab33c9 Mon Sep 17 00:00:00 2001 From: Przemyslaw Wirkus Date: Mon, 28 Sep 2020 15:37:50 +0100 Subject: [PATCH] This patch introduces TRBE (Trace Buffer Extension) system registers for the AArch64 architecture. gas * testsuite/gas/aarch64/trbe-invalid.d: New test. * testsuite/gas/aarch64/trbe-invalid.l: New test. * testsuite/gas/aarch64/trbe-invalid.s: New test. * testsuite/gas/aarch64/trbe.d: New test. * testsuite/gas/aarch64/trbe.s: New test. opcodes * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 , TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1. --- gas/ChangeLog | 8 ++++++++ gas/testsuite/gas/aarch64/trbe-invalid.d | 3 +++ gas/testsuite/gas/aarch64/trbe-invalid.l | 2 ++ gas/testsuite/gas/aarch64/trbe-invalid.s | 2 ++ gas/testsuite/gas/aarch64/trbe.d | 21 +++++++++++++++++++++ gas/testsuite/gas/aarch64/trbe.s | 16 ++++++++++++++++ opcodes/ChangeLog | 5 +++++ opcodes/aarch64-opc.c | 8 ++++++++ 8 files changed, 65 insertions(+) create mode 100644 gas/testsuite/gas/aarch64/trbe-invalid.d create mode 100644 gas/testsuite/gas/aarch64/trbe-invalid.l create mode 100644 gas/testsuite/gas/aarch64/trbe-invalid.s create mode 100644 gas/testsuite/gas/aarch64/trbe.d create mode 100644 gas/testsuite/gas/aarch64/trbe.s diff --git a/gas/ChangeLog b/gas/ChangeLog index b58a2240b1c..565c131965b 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,11 @@ +2020-09-28 Przemyslaw Wirkus + + * testsuite/gas/aarch64/trbe-invalid.d: New test. + * testsuite/gas/aarch64/trbe-invalid.l: New test. + * testsuite/gas/aarch64/trbe-invalid.s: New test. + * testsuite/gas/aarch64/trbe.d: New test. + * testsuite/gas/aarch64/trbe.s: New test. + 2020-09-28 Alex Coplan * config/tc-arm.c (arm_cpus): Add FP16 to Neoverse V1. diff --git a/gas/testsuite/gas/aarch64/trbe-invalid.d b/gas/testsuite/gas/aarch64/trbe-invalid.d new file mode 100644 index 00000000000..a14c15edf02 --- /dev/null +++ b/gas/testsuite/gas/aarch64/trbe-invalid.d @@ -0,0 +1,3 @@ +#name: Invalid TRBE System registers usage +#source: trbe-invalid.s +#warning_output: trbe-invalid.l diff --git a/gas/testsuite/gas/aarch64/trbe-invalid.l b/gas/testsuite/gas/aarch64/trbe-invalid.l new file mode 100644 index 00000000000..c4865c5d9e1 --- /dev/null +++ b/gas/testsuite/gas/aarch64/trbe-invalid.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: specified register cannot be written to at operand 1 -- `msr trbidr_el1,x0' diff --git a/gas/testsuite/gas/aarch64/trbe-invalid.s b/gas/testsuite/gas/aarch64/trbe-invalid.s new file mode 100644 index 00000000000..a37b5851751 --- /dev/null +++ b/gas/testsuite/gas/aarch64/trbe-invalid.s @@ -0,0 +1,2 @@ +/* Write to R/O system register. */ +msr trbidr_el1, x0 diff --git a/gas/testsuite/gas/aarch64/trbe.d b/gas/testsuite/gas/aarch64/trbe.d new file mode 100644 index 00000000000..04b83fb0639 --- /dev/null +++ b/gas/testsuite/gas/aarch64/trbe.d @@ -0,0 +1,21 @@ +#name: TRBE System registers +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: +.*: d5389b40 mrs x0, trbbaser_el1 +.*: d5389be0 mrs x0, trbidr_el1 +.*: d5389b00 mrs x0, trblimitr_el1 +.*: d5389b80 mrs x0, trbmar_el1 +.*: d5389b20 mrs x0, trbptr_el1 +.*: d5389b60 mrs x0, trbsr_el1 +.*: d5389bc0 mrs x0, trbtrg_el1 +.*: d5189b40 msr trbbaser_el1, x0 +.*: d5189b00 msr trblimitr_el1, x0 +.*: d5189b80 msr trbmar_el1, x0 +.*: d5189b20 msr trbptr_el1, x0 +.*: d5189b60 msr trbsr_el1, x0 +.*: d5189bc0 msr trbtrg_el1, x0 diff --git a/gas/testsuite/gas/aarch64/trbe.s b/gas/testsuite/gas/aarch64/trbe.s new file mode 100644 index 00000000000..bf48ed16a31 --- /dev/null +++ b/gas/testsuite/gas/aarch64/trbe.s @@ -0,0 +1,16 @@ +/* Read from system register. */ +mrs x0, trbbaser_el1 +mrs x0, trbidr_el1 +mrs x0, trblimitr_el1 +mrs x0, trbmar_el1 +mrs x0, trbptr_el1 +mrs x0, trbsr_el1 +mrs x0, trbtrg_el1 + +/* Write to system register. */ +msr trbbaser_el1, x0 +msr trblimitr_el1, x0 +msr trbmar_el1, x0 +msr trbptr_el1, x0 +msr trbsr_el1, x0 +msr trbtrg_el1, x0 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 307194dad5e..291c52e54b8 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2020-09-28 Przemyslaw Wirkus + + * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 , + TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1. + 2020-09-26 Alan Modra * csky-opc.h: Formatting. diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 22d69347946..1be8d21642b 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4311,6 +4311,14 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_V8_R ("prselr_el2", CPENC (3,4,C6,C2,1), 0), SR_V8_R ("vsctlr_el2", CPENC (3,4,C2,C0,0), 0), + SR_CORE("trbbaser_el1", CPENC (3,0,C9,C11,2), 0), + SR_CORE("trbidr_el1", CPENC (3,0,C9,C11,7), F_REG_READ), + SR_CORE("trblimitr_el1", CPENC (3,0,C9,C11,0), 0), + SR_CORE("trbmar_el1", CPENC (3,0,C9,C11,4), 0), + SR_CORE("trbptr_el1", CPENC (3,0,C9,C11,1), 0), + SR_CORE("trbsr_el1", CPENC (3,0,C9,C11,3), 0), + SR_CORE("trbtrg_el1", CPENC (3,0,C9,C11,6), 0), + { 0, CPENC (0,0,0,0,0), 0, 0 } }; -- 2.30.2