From 2025a48d089d09011b60c1f5eb981ef71c79be4e Mon Sep 17 00:00:00 2001 From: Peter Bergner Date: Wed, 10 Jan 2018 14:49:36 -0600 Subject: [PATCH] re PR target/83399 (Power8 ICE During LRA with 2-op rtl pattern for lvx instruction) gcc/ PR target/83399 * config/rs6000/rs6000.c (print_operand) <'y'>: Use VECTOR_MEM_ALTIVEC_OR_VSX_P. * config/rs6000/vsx.md (*vsx_le_perm_load_ for VSX_D): Use indexed_or_indirect_operand predicate. (*vsx_le_perm_load_ for VSX_W): Likewise. (*vsx_le_perm_load_v8hi): Likewise. (*vsx_le_perm_load_v16qi): Likewise. (*vsx_le_perm_store_ for VSX_D): Likewise. (*vsx_le_perm_store_ for VSX_W): Likewise. (*vsx_le_perm_store_v8hi): Likewise. (*vsx_le_perm_store_v16qi): Likewise. (eight unnamed splitters): Likewise. gcc/testsuite/ PR target/83399 * gcc.target/powerpc/pr83399.c: New test. From-SVN: r256453 --- gcc/ChangeLog | 16 +++++++++++ gcc/config/rs6000/rs6000.c | 2 +- gcc/config/rs6000/vsx.md | 32 +++++++++++----------- gcc/testsuite/ChangeLog | 5 ++++ gcc/testsuite/gcc.target/powerpc/pr83399.c | 15 ++++++++++ 5 files changed, 53 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr83399.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ab2c2cca52c..7a989b42c4c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2018-01-10 Peter Bergner + + PR target/83399 + * config/rs6000/rs6000.c (print_operand) <'y'>: Use + VECTOR_MEM_ALTIVEC_OR_VSX_P. + * config/rs6000/vsx.md (*vsx_le_perm_load_ for VSX_D): Use + indexed_or_indirect_operand predicate. + (*vsx_le_perm_load_ for VSX_W): Likewise. + (*vsx_le_perm_load_v8hi): Likewise. + (*vsx_le_perm_load_v16qi): Likewise. + (*vsx_le_perm_store_ for VSX_D): Likewise. + (*vsx_le_perm_store_ for VSX_W): Likewise. + (*vsx_le_perm_store_v8hi): Likewise. + (*vsx_le_perm_store_v16qi): Likewise. + (eight unnamed splitters): Likewise. + 2018-01-10 Peter Bergner * config/rs6000/x86intrin.h: Change #warning to #error. Update message. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index a6f3e4e0d0a..f3df0b98462 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -21671,7 +21671,7 @@ print_operand (FILE *file, rtx x, int code) tmp = XEXP (x, 0); - if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x)) + if (VECTOR_MEM_ALTIVEC_OR_VSX_P (GET_MODE (x)) && GET_CODE (tmp) == AND && GET_CODE (XEXP (tmp, 1)) == CONST_INT && INTVAL (XEXP (tmp, 1)) == -16) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index effa6c1103e..e0d76b1e382 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -431,7 +431,7 @@ ;; VSX moves so they match first. (define_insn_and_split "*vsx_le_perm_load_" [(set (match_operand:VSX_D 0 "vsx_register_operand" "=") - (match_operand:VSX_D 1 "memory_operand" "Z"))] + (match_operand:VSX_D 1 "indexed_or_indirect_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" @@ -454,7 +454,7 @@ (define_insn_and_split "*vsx_le_perm_load_" [(set (match_operand:VSX_W 0 "vsx_register_operand" "=") - (match_operand:VSX_W 1 "memory_operand" "Z"))] + (match_operand:VSX_W 1 "indexed_or_indirect_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" @@ -479,7 +479,7 @@ (define_insn_and_split "*vsx_le_perm_load_v8hi" [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa") - (match_operand:V8HI 1 "memory_operand" "Z"))] + (match_operand:V8HI 1 "indexed_or_indirect_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" @@ -508,7 +508,7 @@ (define_insn_and_split "*vsx_le_perm_load_v16qi" [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa") - (match_operand:V16QI 1 "memory_operand" "Z"))] + (match_operand:V16QI 1 "indexed_or_indirect_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" @@ -544,7 +544,7 @@ (set_attr "length" "8")]) (define_insn "*vsx_le_perm_store_" - [(set (match_operand:VSX_D 0 "memory_operand" "=Z") + [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "=Z") (match_operand:VSX_D 1 "vsx_register_operand" "+"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" @@ -552,7 +552,7 @@ (set_attr "length" "12")]) (define_split - [(set (match_operand:VSX_D 0 "memory_operand" "") + [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "") (match_operand:VSX_D 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) @@ -571,7 +571,7 @@ ;; The post-reload split requires that we re-permute the source ;; register in case it is still live. (define_split - [(set (match_operand:VSX_D 0 "memory_operand" "") + [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "") (match_operand:VSX_D 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) @@ -589,7 +589,7 @@ "") (define_insn "*vsx_le_perm_store_" - [(set (match_operand:VSX_W 0 "memory_operand" "=Z") + [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "=Z") (match_operand:VSX_W 1 "vsx_register_operand" "+"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" @@ -597,7 +597,7 @@ (set_attr "length" "12")]) (define_split - [(set (match_operand:VSX_W 0 "memory_operand" "") + [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "") (match_operand:VSX_W 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) @@ -618,7 +618,7 @@ ;; The post-reload split requires that we re-permute the source ;; register in case it is still live. (define_split - [(set (match_operand:VSX_W 0 "memory_operand" "") + [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "") (match_operand:VSX_W 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) @@ -639,7 +639,7 @@ "") (define_insn "*vsx_le_perm_store_v8hi" - [(set (match_operand:V8HI 0 "memory_operand" "=Z") + [(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "=Z") (match_operand:V8HI 1 "vsx_register_operand" "+wa"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" @@ -647,7 +647,7 @@ (set_attr "length" "12")]) (define_split - [(set (match_operand:V8HI 0 "memory_operand" "") + [(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "") (match_operand:V8HI 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) @@ -672,7 +672,7 @@ ;; The post-reload split requires that we re-permute the source ;; register in case it is still live. (define_split - [(set (match_operand:V8HI 0 "memory_operand" "") + [(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "") (match_operand:V8HI 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) @@ -699,7 +699,7 @@ "") (define_insn "*vsx_le_perm_store_v16qi" - [(set (match_operand:V16QI 0 "memory_operand" "=Z") + [(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "=Z") (match_operand:V16QI 1 "vsx_register_operand" "+wa"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" @@ -707,7 +707,7 @@ (set_attr "length" "12")]) (define_split - [(set (match_operand:V16QI 0 "memory_operand" "") + [(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "") (match_operand:V16QI 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) @@ -740,7 +740,7 @@ ;; The post-reload split requires that we re-permute the source ;; register in case it is still live. (define_split - [(set (match_operand:V16QI 0 "memory_operand" "") + [(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "") (match_operand:V16QI 1 "vsx_register_operand" ""))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6091e59998b..5fdb4701b06 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-01-10 Peter Bergner + + PR target/83399 + * gcc.target/powerpc/pr83399.c: New test. + 2018-01-10 David Malcolm PR c++/43486 diff --git a/gcc/testsuite/gcc.target/powerpc/pr83399.c b/gcc/testsuite/gcc.target/powerpc/pr83399.c new file mode 100644 index 00000000000..96d9b382184 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr83399.c @@ -0,0 +1,15 @@ +/* PR target/83399 */ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O1 -mabi=elfv2 -mlittle -mvsx" } */ + +typedef __attribute__((altivec(vector__))) int v4si_t; +int +foo (void) +{ + v4si_t a, u, v, y; + u = __builtin_altivec_lvx (32, ((void *) &a) - 32); + v = __builtin_altivec_lvx (64, ((void *) &a) - 32); + y = u + v; + return y[0]; +} -- 2.30.2